George Nychis wrote:
We want to compute the RSSI in dB on the FPGA, we're not even
interested in the FPGA responding back with the RSSI at this point.
Okay, but--why do you need units of dB? This is in the log domain, so
at some point on the FPGA you'll need to take a logarithm of an
amplitude. If it is for the user's benefit, then it is much simpler to
do the conversion on the host.
1. What exact information needs to be shared?
The output of the ADC is a fixed multiple of the signal at the antenna
input. Since the gain settings are controlled by the host, the host
would need to calculate what the overall gain is and poke a register
with a value the FPGA logic could use.
Again, though, why do you need to get the actual RSSI? If you're going
to use it for carrier-sense, then all you really need to do is threshold
the average magnitude of the ADC output. You've already got that value
calculated in rssi.v (perhaps that's a confusing name for the Verilog file.)
The only downside of rssi.v output is that the time constant for
averaging is fixed (to make the logic very simple, fast, and low-area.)
2. Where can we get the information? I'm assuming when the
daughterboards are initialized most of this information is available.
It would be different for each daughterboard, but code could be added to
the host daughterboard handling code to determine the overall antenna to
ADC gain when the gain settings are set by the user. That overall gain
value would then be poked into a register on the FPGA to be used by your
code to get actual antenna power (assuming you still really need to do
this.)
Finally, for an AGC, the power measurement portion of the control loop
doesn't need to be taken all the way to dB.