Re: [Discuss-gnuradio] A Verilog question or two

[Brian Padalino]

On Tue, Oct 14, 2008 at 10:45 AM, Sebastiaan Heunis <address@hidden> wrote:
> Hi
>
> Can someone with Verilog experience please help me with a question or
> two?  I have done some VHDL before, so I am not entirely clueless.
>
> Is it possible to bit selects with an array of registers?  How do I
> select the upper eight bits from ram_array[2] if I have the following?
>
> reg [15:0]              ram_array [0:15];

Using my Google prowess:

    http://www.geda.seul.org/mailinglist/geda-dev33/msg00056.html

> The difference between
>
> val <= #1 input[15:12]; and
> val = input[15:12];
>
> when it is inside an always @(posedge clk) block is that the = sign
> operation is sequential, right and that <= operations are in parallel?
> The #1 means a delay of 1, right?  So if I for instance have data
> going through a filter with the following code
>
> always @(posedge clk)
> begin
>  tap1 <= #1 input;
>  tap2 <= #1 tap1;
>  tap3 <= #1 tap2;
> end
>
> the #1 ensures that tap1 gets updated before tap2?
>
> And the last question is regarding the assign statement.  I know that
> when we have commands inside a always @(posedge clk) block, we look at
> clock changes and do certain things.  Do we use the assign statement
> if we for instance want to change an output when in input changes or
> if we have an output that is not dependent on a clock?  I still don't
> exactly know when to use an assign instead if putting it inside an
> always block?  What's the rule of thumb?

Here area couple good pages to read about all that:

    http://www.asic-world.com/verilog/verilog_one_day3.html
    http://www.asic-world.com/verilog/timing_ctrl1.html

> Thanks in advance.

You're welcome.

Brian