Re: [Discuss-gnuradio] A Verilog question or two

[Daniel O'Connor]

On Wednesday 15 October 2008 01:15:48 Sebastiaan Heunis wrote:
> always @(posedge clk)
> begin
>  tap1 <= #1 input;
>  tap2 <= #1 tap1;
>  tap3 <= #1 tap2;
> end
>
> the #1 ensures that tap1 gets updated before tap2?

According to what I have read with about synthesis tools the delays will be 
ignored totally.

I see a lot of it though, so I don't know if it's superstition or the manual 
lies.

The above code will do those 3 assignments simultaneously.

I found the following to be very very useful in explaining things in detail 
without getting bogged down in the useless level of crud you find in a lot of 
text books (eg how CMOS gates are made..) http://web.mit.edu/6.111/www/f2005/

> And the last question is regarding the assign statement.  I know that
> when we have commands inside a always @(posedge clk) block, we look at
> clock changes and do certain things.  Do we use the assign statement
> if we for instance want to change an output when in input changes or
> if we have an output that is not dependent on a clock?  I still don't
> exactly know when to use an assign instead if putting it inside an
> always block?  What's the rule of thumb?

always @(posedge clk) will only cause things to change on the positive edge of 
clk (like it says :) - using assign will cause things to change at any time. 
(sequential vs combinational). You can also do combinational logic inside an 
always block (see page 5 onwards of L04 above).

PS I am far from a Verilog guru so if there is one reading please correct any 
mistakes I have made :)

-- 
Daniel O'Connor software and network engineer
for Genesis Software - http://www.gsoft.com.au
"The nice thing about standards is that there
are so many of them to choose from."
  -- Andrew Tanenbaum
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