[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Discuss-gnuradio] Using the MIMO port for serial comm. to a Virtex

From: Charles Irick
Subject: Re: [Discuss-gnuradio] Using the MIMO port for serial comm. to a Virtex5 board
Date: Tue, 1 Dec 2009 15:58:35 -0500

I'm most likely having a clock issue because I cannot get any data
transfers going between the USRP2 and GTPs on the V5. A few questions:

- I'm not quite sure I understand the 10MHz reference clock idea, or
its usage; I looked through the HDL and everything on the FPGA is
running at 100MHz.

- I assume I will not need to provide this reference clock if the
USRP2 is the driver given that sd_gentest appears to do so in the main
functions clocks_mimo_config. Either way I'm using the SAS to quad
SATA cable so the clock isn't even transferred to the GTPs (literally,
it's supposed to derive it from the data).

- My only clocking options on the GTP's are 150 or 75MHz. I'm not sure
if I should clock the USRP2's FPGA or the reference differently to
match this.

Any help with the clocking scheme would be much appreciated. Thank you.


On Fri, Nov 27, 2009 at 4:20 PM, Charles Irick <address@hidden> wrote:
> On Thu, Nov 26, 2009 at 4:47 PM, Matt Ettus <address@hidden> wrote:
>> Yes, you'll need to do firmware.  If you just modify the main() function to
>> set the loopback, it doesn't matter which firmware you start with.
> The closest thing I can find is the following:
> output_regs->serdes_ctrl = (SERDES_ENABLE | SERDES_RXEN |
> I tried pasting that line into main() of sd_bounce assuming that
> SERDES_LOOPEN was the loopback parameter.
> I'm not getting anything back on the V5 side so if that function is
> correct then it is probably some type of clocking issue.
>> BTW, I don't know how you intended to physically connect the boards. The
>> best long term solution is to have your own custom board which implements
>> the connections we use (SAS).  In the short term, you can buy a SAS to quad
>> SATA breakout cable.  This would connect right to the SATA headers on many
>> FPGA eval boards.
>> Matt
> Right now this is what I'm doing. SAS to quad SATA breakout. I'm using
> Lane 1 to connect to the V5 board. Are there any particular
> disadvantages to this solution that made you suggest a custom board?
> Charles

reply via email to

[Prev in Thread] Current Thread [Next in Thread]