On 12/01/2009 12:58 PM, Charles Irick wrote:
I'm most likely having a clock issue because I cannot get any data
transfers going between the USRP2 and GTPs on the V5. A few questions:
- I'm not quite sure I understand the 10MHz reference clock idea, or
its usage; I looked through the HDL and everything on the FPGA is
running at 100MHz.
The 10 MHz reference input on the front is optional. If you connect it
enable locking, the 100 MHz main oscillator will lock to it, otherwise it
will free run. Everything inside the FPGA runs at 100 MHz (DSP) or 50
There is also a 10 MHz reference clock sent out on the MIMO connector.
turned on, it will be the 100 MHz clock divided down by 10.
- I assume I will not need to provide this reference clock if the
USRP2 is the driver given that sd_gentest appears to do so in the main
functions clocks_mimo_config. Either way I'm using the SAS to quad
SATA cable so the clock isn't even transferred to the GTPs (literally,
it's supposed to derive it from the data).
sd_gentest will generate packets and send them on the serdes on the MIMO
cable. You should be able to receive it without using the 10 MHz
clock because, as you say, the clock is recovered from the data.
- My only clocking options on the GTP's are 150 or 75MHz. I'm not sure
if I should clock the USRP2's FPGA or the reference differently to
The important thing is that you get the GTPs set up for the correct data
rate. On the USRP2, the main clock to the SERDES chip is 100 MHz. 2
are sent on each clock, so the effective data rate is 1.6 Gbps. However,
since 8b-10b coding is used, the on the wire bit rate is 2.0 Gbps
(20*100MHz). So whatever reference clock you use, you need the GTP to be
working at 2 Gbps. I am by no means an expert on the GTPs, but I think
easiest way to do this is to have a reference clock of 100 MHz.
You could probably use the PLLs in the V5 to create a 100 MHz reference
clock from one of your other clock rates.