Dear all,
I'm reading the receiver part of gr-sounder project. As my undering, in the FPGA configuration of this project, the received signal directly goes to the sounder module, after being demuxed into I and Q signals by adc_interface module. I didn't see any module of the FPGA configuration of this project implments DDC. In python program, however, it has been set the tunning frequency for sounder receiver. Which part of the receiver tunning frequency will set to in the FPGA configuration? Which part of the FPGA configuration implements DDC?
Thank you so much in advance.
Yan
ynie3.vcf