[Discuss-gnuradio] interfacing a DSP array card to USRP2

[Jeff Brower]

Matt-

We're working on a project at Signalogic to interface one of our DSP array PCIe 
cards to the USRP2.  This would
provide a way for one or more TI DSPs to "insert" into the data flow and run 
C/C++ code for low-latency and/or other
high performance applications.  The idea is that we would modify the current 
USRP2 driver (or create an alternative)
so it would read/write to/from the PCIe card instead of the Linux (motherboard) 
GbE.

A few general questions at this point:

1) We would connect the USRP2 to the GbE on our DSP array card.  We would want 
to shift latency/delay "downstream" to
the PCIe card Linux driver interface, and make the GbE-to-GbE interface as low 
latency as possible.  Could you give us
some guidance on which FPGA modules handle buffering for host transmit/receive? 
 Is it reasonable we can reduce buffer
sizes if the array card GbE has a fast response time?

2) We want to use the GNU radio GMAC as opposed to Xilinx or other 
off-the-shelf core, our thinking being that we can
make contributions to data rate and latency-reduction discussions, as well as 
tech USRP2 tech support, if we become
familiar with your core.  Can you give us some guidance on a process to remove 
non-GMAC related modules from the
firmware?  Go to the top level and start pulling?  Obviously SRAM related, 
CORDIC, and ADC/DAC interfaces, are not
needed.

3) Do you have an FPGA internal achitecture block diagram of any type?  Is 
there another group you're aware of doing
such "major modification" FPGA work that we might talk to?

Thanks.

-Jeff