[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Discuss-gnuradio] Costum FPGA in E310

From: linux
Subject: [Discuss-gnuradio] Costum FPGA in E310
Date: Sat, 11 Apr 2015 13:41:05 -0400

Hi all,

I am actually working on a project needs migrate an old FPGA program to E310. First, I want to custom the official FPGA program of E310. But I found some configurations of PS are not the same on the schematics diagram. And I tried to export to SDK, but even the simple hello world program didn't work.

I listed what I have done as follow:

1. first, I downloaded the FPGA source code from this address: https://github.com/EttusResearch/fpga/tree/master 

2. I taped these commands to build the project:
$source /opt/Xilinx/14.7/ISE_DS/setting64.sh
$export PATH=$PATH: /opt/Xilinx/14.7/ISE_DS/ISE/bin/bin/lin64/xtclsh
$cd fpga-master/usrp3/top/e300
$make E310

3. This step took about 1 hour. And then, I open the XPS project.
$cd build-E310/zynq-ps
$xps e300_ps.xmp

4. The XPS was just opened. But from here I found some settings I don’t understand. In the ZYNQ PS CONFIGURATION, the UART1 was selected using MIO 48 … 49, but in the schematic diagram of USRP E300 series Motherboard, the UART was using UART0. And UART0 used MIO 14 and MIO 15.

5. If I tried to generate the bitstream from this XPS project, it will give me a lot of errors like:

ERROR:MapLib:979 - LUT6 symbol

"axi_interconnect_1/axi_interconnect_1/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT.read_addr_inst/Madd_M_AXI_AADDR_I[31]_GND_19_o_add_51_OUT_lut<10>" (output signal=axi_interconnect_1/axi_interconnect_1/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT.read_addr_inst/Madd_M_AXI_AADDR_I[31]_GND_19_o_add_51_OUT_lut<10>) has input signal "axi_interconnect_1/axi_interconnect_1/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT.read_addr_inst/S_AXI_AADDR_Q<10>" which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven.

6. Finally, I exported design to SDK with no bitstream, but even the simple Hello world print program didn't work. There was nothing output from the UART port.

I want know if there is someone have done a similar work who can tell me where am I doing wrong?


Weidong Wang


reply via email to

[Prev in Thread] Current Thread [Next in Thread]