|Subject:||Re: [Discuss-gnuradio] Costum FPGA in E310|
|Date:||Wed, 15 Apr 2015 10:34:23 -0500|
Hi Moritz,Thanks for your reply.I need to migrate a project realized on virtix4 to E310. This project has custom ip code of digital signal process on the both side of PS and PL. And we use the standalone system in Microblaze.If I don't misunderstand you, you mean the fpga project which I downloaded from git can be modified only in the PL? Is it possible I could get a version of XPS project I can custom my own design on the both side PS and PL?Thanks again,On 2015-04-12, at 14:03, Moritz Fischer wrote:Hi Weidong,
the XPS project that's made during the current E310 build is not meant
to be used to implement custom designs.
We usually just add stuff to the Makefiles (custom RTL, coregen files,
etc). If you can give us some more info on what you're trying to do,
we'll be able to help you out better.
On Sat, Apr 11, 2015 at 10:41 AM, linux
<address@hidden> wrote:Hi all,I am actually working on a project needs migrate an old FPGA program toE310. First, I want to custom the official FPGA program of E310. But I foundsome configurations of PS are not the same on the schematics diagram. And Itried to export to SDK, but even the simple hello world program didn't work.I listed what I have done as follow:1. first, I downloaded the FPGA source code from this address:2. I taped these commands to build the project:$source /opt/Xilinx/14.7/ISE_DS/setting64.sh$export PATH=$PATH: /opt/Xilinx/14.7/ISE_DS/ISE/bin/bin/lin64/xtclsh$cd fpga-master/usrp3/top/e300$make E3103. This step took about 1 hour. And then, I open the XPS project.$cd build-E310/zynq-ps$xps e300_ps.xmp4. The XPS was just opened. But from here I found some settings I don’tunderstand. In the ZYNQ PS CONFIGURATION, the UART1 was selected using MIO48 … 49, but in the schematic diagram of USRP E300 series Motherboard, theUART was using UART0. And UART0 used MIO 14 and MIO 15.5. If I tried to generate the bitstream from this XPS project, it will giveme a lot of errors like:ERROR:MapLib:979 - LUT6 symbol"axi_interconnect_1/axi_interconnect_1/mi_protocol_conv_bank/gen_protocol_slot.gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT.read_addr_inst/Madd_M_AXI_AADDR_I_GND_19_o_add_51_OUT_lut<10>"(outputsignal=axi_interconnect_1/axi_interconnect_1/mi_protocol_conv_bank/gen_protocol_slot.gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT.read_addr_inst/Madd_M_AXI_AADDR_I_GND_19_o_add_51_OUT_lut<10>)has input signal"axi_interconnect_1/axi_interconnect_1/mi_protocol_conv_bank/gen_protocol_slot.gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT.read_addr_inst/S_AXI_AADDR_Q<10>"which will be trimmed. See Section 5 of the Map Report File for detailsabout why the input signal will become undriven.6. Finally, I exported design to SDK with no bitstream, but even the simpleHello world print program didn't work. There was nothing output from theUART port.I want know if there is someone have done a similar work who can tell mewhere am I doing wrong?Thanks,Weidong Wang_______________________________________________Discuss-gnuradio mailing list
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