The release candidate
of UHD version 3.13.1.0 has been tagged and is available for testing. There were several issues found and fixed since the 3.13.0.3 release candidate. Those changes resulted in an ABI incompatibility, so there will be no 3.13.0.3 release. All the commits for the former 3.13.0.3 release candidate are included in this release candidate.
This release candidate is API compatible all 3.13 releases.
The tag for this
release:
https://github.com/EttusResearch/uhd/releases/tag/v3.13.1.0-rc1There have been 86 commits since the 3.13.0.2
release which can be viewed here:
Please report any bugs found on the UHD issue tracker:
* Please do not use the issue tracker for help or support.
Pull requests for direct code changes can be submitted to the UHD or FPGA repositories:
CHANGELOG:
## 003.013.001.000
* E320: Fix front panel GPIO readback
* E320: Fix master_clock_rate setting
* E320: Print extra ouptut for ref_clock BIST
* N3xx: Enable setting clock and time sources at runtime
* N3xx: Add ref_clock BIST
* N3xx: Improve set_time_source() and set_clock_source()
* N3xx: Add exception for init failure
* N310: Add frequency bounds
* N310: Fix RX antenna mapping
* N310: Add log messages when re-initializing dboards
* N310: Add skip_rfic argument to reduce time of BIST
* X300: Improve firmware compat error message
* X300: Updated niusrprio driver
* X300: Add recovery for duplicate IP addresses in EEPROM
* X300: Prevent duplicate MAC and IP addresses from being programmed
* B2xx: Fix values of MASK_GPIO_SHDN_SW and GPIO_AUX_PWR_ON in firmware
* B2xx: Revert changes to DSP core to fix scaling factor adjustment
* B2xx: Restore asynchronous reset of AD936x
(fixes LIBUSB_TRANSFER_OVERFLOW and unexpected sid errors)
* TwinRX: enable ch1 lo amps if ch2 is using an external lo source
* TwinRX: Correctly initialize antenna mapping on X300
* TwinRX: Revise ADF5356 frac2 register calculation to prevent drifting spurs
* BasicRX/LFRX: Fix real mode in rx_frontend_core_3000
* UHD: Define UHD_API as empty string when building static lib
* UHD: Changed to 'all_matching' endpoint resolution for udp_simple transport
* UHD: Add support for NEON SIMD
* UHD: Fix usb_dummy_impl compilation in MSVC
* UHD: Reconcile time_spec operators with boost concepts
* UHD: Fix rounding in ddc/duc rate calculation
* UHD: Increase MPMD RPC timeout when calling set_time_source()
* UHD: Fix RX streamer SOB and EOB handling
* UHD: Add UHD_SAFE_CALL to block_ctrl_base destructor
* UHD: Change SOVERSION to ABI string and VERSION to full UHD version
* RFNoC: Improved flushing mechanism in noc_shell and dma_fifo
* RFNoC: Install missing dma_fifo_block_ctrl header
* MPM: Add Git hash, version to device info
* MPM: Reset the RPC server upon reload
* MPM: TDC: Update PDAC BIST and flatness test to use latest APIs
* MPM: Fix handling of 0-valued dt-compat
* MPM: Fix GPSD sensor names for N3xx and E320
* MPM: Add args to update_ref_clock_freq to properly support dynamic setting
* of clock and time references
* MPM: Fix Pylint warnings
* MPM: Identify sysfs gpios more generically
* MPM: Add lock_guard() function
* MPM: Factor E320 and N3xx BIST code into common module
* Python API: Enable Python API on Windows
* Python API: Change .dll to .pyd for Win32
* Python API: Fixing Boost.Python initializer visibility
* Python API: Fix duration of benchmark rate
* Python API: Add missing constructors of time_spec_t
* Utils: Fix uhd_images_downloader to properly refetch when upgrading/downgrading
* Utils: Added logging for case of no targets selected in uhd_images_downloader
* Examples: Removed some legacy code patterns from RFNoC examples
* Examples: Fix channel argument for rx_samples_to_file
* Examples: Fix benchmark_rate MIMO synchronization
* Test: Add more env vars, make Py3k compatible
* Test: Add multi_usrp_test.py to devtest
* Test: Clean up, refactor, and improve devtest
* Test: Enable rx_samples_to_file in E320 devtest and N3xx devtest
* Test: Reduce sample rate for E320 1G devtest
* Test: Add unit test for eeprom_utils
* Docs: Add clock_source and time_source to n3xx argument list and fix WR clock_source call
* Docs: Minor tweaks to the Python API manual page
* Docs: Add E320 test procedures
* Docs: Added TwinRX page
* Docs: Fix N210 MIMO Phase Alignment test command
* Docs: Add E320 information
* Docs: Improve sections on clock/time references
* Debian: Update control files
We at Ettus Research would like to thank all of the UHD users
in the open source SDR community. This release contains commits from users in the community that submitted pull requests
against the
UHD and
FPGA
repositories. Most of the other fixes and enhancements in this release candidate are a direct result of issues reported back to us by you
through the
UHD and
FPGA
issue trackers, the USRP-users mailing list, and
Ettus support. You have all helped contribute to the continued improvement of
UHD. Thank you!
Best regards,