Re: [Help-gnucap] gnucap with verilog-ams netlist input

[al davis]

On Sunday 25 January 2009, John Griessen wrote:
> How do I connect a gnucap internal capacitor model to this
> netlist generated by gnetlist -g verilog?

some things don't work yet.

> /* structural Verilog generated by gnetlist */
> /* WARNING: This is a generated file, edits */
> /*        made here will be lost next time  */
> /*        you run gnetlist!                 */
> /* Id ..........$Id$ */
> /* Source.......$Source$ */
> /* Revision.....$Revision$ */
> /* Author.......$Author$ */

like /* */ comments
>
> module verilog_io (    GND ,    C ,    A  );

> /* Port directions begin here */
> inout GND ;
> inout C ;
> inout A ;

declarations don't work.
In real Verilog, they are optional if only structure is used.
"inout" and "electrical" are assumed,
but really they are only used for type checking.

> /* Package instantiations */
> cap #(.value(1250e-9) ) C1 ( .p(B), .n(GND));

It's "capacitor" and the name of the value is "c".

> ind #(.l(.001) ) L1 ( .n(C), .p(B));
"inductor", the name of the value is "l". (lower case..)

> res #(.r(1000) ) R1 ( .n(B), .p(A));
"resistor", the name of the value is "r".

> endmodule

If there is only one number that is thought of as the "value", 
you can specify it with name.

capacitor #(1u) C4 (f,r);