[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] [ADD] PPC processor emulation

From: Gwenole Beauchesne
Subject: Re: [Qemu-devel] [ADD] PPC processor emulation
Date: Tue, 18 Nov 2003 13:24:01 +0100 (CET)

On Tue, 18 Nov 2003, J. Mayer wrote:

> > I have a test program that covers around 600K variants with specific
> > values to trigger flags updates. It requires a PPC host for now to
> > validate results. It helped a lot to first write a correct interpreter and
> > discover some hidden semantics in rare cases.
> > 
> The program, ppc_test does this with a lot of different instruction,
> using a huge set of values. With the ctrace program, I could check that
> it runs the same on my Ibook and on my PC with qemu. Where could I find
> yours to make more tests ?

An oldish version is available here:

I will commit a newer version tonight. The "JIT1" engine is not committed
yet either.

> You found hidden semantics, as you say. What is confusing, also, is that
> Motorola's implementation isn't the same than IBM's one for some strange
> cases...

Nevermind, you got divw implementation right at first sight, so forget 
about it. ;-)

> My TBL/TBU implementation isn't a real time clock, but is a cycle
> counter, as on "real" PPC.

Doesn't a real PPC increments TBR after a time comparable to at least 4 
addi instructions? I think there was an Apple TN# about it.

> That means that the CPU will seem to run with a variable clock, if a
> program compares its value to the one given by a real-time clock. It's
> updated at the end of a translated block, or when I see a mftbl/mftbu
> instruction.

Sounds reasonable.


reply via email to

[Prev in Thread] Current Thread [Next in Thread]