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Re: [Qemu-devel] [PATCH] SH: Add prefi, icbi, synco

From: Paul Brook
Subject: Re: [Qemu-devel] [PATCH] SH: Add prefi, icbi, synco
Date: Mon, 20 Oct 2008 11:54:20 +0100
User-agent: KMail/1.9.9

On Monday 20 October 2008, Paul Mundt wrote:
> On Fri, Oct 17, 2008 at 08:56:52PM +0100, Paul Brook wrote:
> > On Friday 17 October 2008, Vladimir Prus wrote:
> > > This patch makes qemu recognize (and ignore), three instructions from
> > > SH4A.
> >
> > Shouldn't these generate an illegal instruction exception on SH4 cpus?
> Note that all of these are SH-5 instructions, which gradually found their
> way in to the SH-4A ISA. There are also other SH-5 instructions that have
> found their way in to the SH-2A ISA which are not as of yet reflected in
> SH-4A. The dependency tracking gets to be pretty ugly, as is evident in
> binutils. In order to get this right, it would be necessary to throw ISA
> versioning in to the CPU definition and test to figure out what to
> support, as per the table in binutils. While this would be a good idea in
> general, it is something that should be done as a larger follow-up to
> these patches.

I disagree. This is something that should be done right from the start. Trying 
to fix it up later is a real pain.  Doing fine grained features isn't that 
hard. MIPS, sparc, arm, ppc, m68k and sparc already do this. IIRC binutils is 
only complicated because it tried to create a strict hieracy of features, 
rather than using feature bits.


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