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Re: [Qemu-devel] [PATCH 15/15] Add bast and smdk2410 boards which use S3
From: |
Ben Dooks |
Subject: |
Re: [Qemu-devel] [PATCH 15/15] Add bast and smdk2410 boards which use S3C2410 SOC |
Date: |
Fri, 15 May 2009 21:29:09 +0100 |
User-agent: |
Mutt/1.5.13 (2006-08-11) |
On Fri, May 15, 2009 at 09:52:57PM +0200, Jean-Christophe PLAGNIOL-VILLARD
wrote:
> On 10:41 Fri 15 May , Vincent Sanders wrote:
> > On Thu, May 14, 2009 at 02:35:19PM +0200, Jean-Christophe PLAGNIOL-VILLARD
> > wrote:
> > > On 09:44 Wed 06 May , Vincent Sanders wrote:
> > > > Signed-off-by: Vincent Sanders <address@hidden>
> > > > ---
> > > tks for the pflash support forhe bast
> > > is it possible to have the same on the smdk2410?
> > >
> > > IIRC there is a 8Mib
> >
> > I would, of course, be happy to accomodate. However I dont have data
> > on where the writable flash copy is mapped.
I've not seen anything in the UBoot sources, and having looked at the
schematic there is an link option to change the ROM nCS from nGCS0 to
nGCS1. However looking at the uboot sources it seems to only use the
nGCS0 addressing.
> > The s3c2410 chip select 0 (where the NOR is booted from) has no write
> > line so a second writable mapping is required (hence the second
> > mapping on the bast).
> >
> > It may turn out the flash cannot be reprogramed with the CPU and the
> > external JTAG boundry scan must be used. If this is the case it really
> > is a ROM mapping from an emulation POV.
> >
> > If anyone can provide information on if/where the smdk2410 writable
> > flash area is I will gladly add it.
> Based on u-boot code
> there is 2 version of the boards
> one with a 8Mbit AMD flash
> and an other one with a 4Mbit AMD flash
>
> map at 0x00000000
> and writeable as the u-boot env is stored at 0xF0000 and 0x70000
>
> Ben could maybe confirm us
The manual says that nGCS0 is read-only, but unfortunately I've not
got an SMDK2410 available to verify that the manual is correct in
this respect. I might still have a board with an S3C2410 on to see
if this can be reproduced by experimentation over the weekend.
> Best Regards,
> J.
--
--
Ben
Q: What's a light-year?
A: One-third less calories than a regular year.
- [Qemu-devel] [PATCH 01/15] Add ARM 920T CPU identifier, (continued)
- [Qemu-devel] [PATCH 01/15] Add ARM 920T CPU identifier, Vincent Sanders, 2009/05/06
- [Qemu-devel] [PATCH 02/15] S3C system on chip integrated peripheral device state header, Vincent Sanders, 2009/05/06
- [Qemu-devel] [PATCH 06/15] Peripheral driver for S3C SOC timers., Vincent Sanders, 2009/05/06
- [Qemu-devel] [PATCH 07/15] Peripheral driver for S3C SOC Serial ports., Vincent Sanders, 2009/05/06
- [Qemu-devel] [PATCH 15/15] Add bast and smdk2410 boards which use S3C2410 SOC, Vincent Sanders, 2009/05/06
[Qemu-devel] [PATCH 14/15] S3C2440 Implementation using S3C periperals., Vincent Sanders, 2009/05/06
[Qemu-devel] [PATCH 13/15] S3C2410 SOC implementation using S3C peripheral blocks., Vincent Sanders, 2009/05/06
[Qemu-devel] [PATCH 12/15] Peripheral driver for S3C SOC NAND controller, Vincent Sanders, 2009/05/06
[Qemu-devel] [PATCH 10/15] Peripheral driver for S3C SOC I2C controller., Vincent Sanders, 2009/05/06
[Qemu-devel] [PATCH 09/15] Peripheral driver for S3C SOC general purpose I/O, Vincent Sanders, 2009/05/06
[Qemu-devel] [PATCH 11/15] Peripheral driver for S3C SOC LCD controller, Vincent Sanders, 2009/05/06
[Qemu-devel] [PATCH 08/15] Peripheral driver for S3C SOC real time clock., Vincent Sanders, 2009/05/06
[Qemu-devel] [PATCH 05/15] Peripheral driver for S3C SOC clock control., Vincent Sanders, 2009/05/06
[Qemu-devel] [PATCH 04/15] Peripheral driver for S3C SOC IRQ controller., Vincent Sanders, 2009/05/06
Re: [Qemu-devel] Add ARM S3C SOC core, drivers and boards, Vincent Sanders, 2009/05/14