[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v2 6/6] arm: Remove incorrect comment in arm_tim
From: |
Andreas Färber |
Subject: |
Re: [Qemu-devel] [PATCH v2 6/6] arm: Remove incorrect comment in arm_timer |
Date: |
Tue, 10 Jan 2012 19:03:01 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:9.0) Gecko/20111220 Thunderbird/9.0 |
Am 10.01.2012 17:45, schrieb Mark Langsdorf:
> The current comment says that the arm_timers are restricted to between
> 32 KHz and 1 MHz, but sp804 TRM does not specify those limits.
>
> Signed-off-by: Mark Langsdorf <address@hidden>
Reviewed-by: Andreas Färber <address@hidden>
Thanks,
Andreas
> ---
> Changes from v1
> Clarified the commit message
>
> hw/arm_timer.c | 3 ---
> 1 files changed, 0 insertions(+), 3 deletions(-)
>
> diff --git a/hw/arm_timer.c b/hw/arm_timer.c
> index 60e1c63..15d493f 100644
> --- a/hw/arm_timer.c
> +++ b/hw/arm_timer.c
> @@ -272,11 +272,8 @@ static int sp804_init(SysBusDevice *dev)
>
> qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
> sysbus_init_irq(dev, &s->irq);
> - /* The timers are configurable between 32kHz and 1MHz
> - * defaulting to 1MHz but overrideable as individual properties */
> s->timer[0] = arm_timer_init(s->freq0);
> s->timer[1] = arm_timer_init(s->freq1);
> -
> s->timer[0]->irq = qi[0];
> s->timer[1]->irq = qi[1];
> memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
- [Qemu-devel] [PATCH v5 3/6] ahci: add support for non-PCI based controllers, (continued)
- [Qemu-devel] [PATCH v5 3/6] ahci: add support for non-PCI based controllers, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v2 5/6] arm: SoC model for Calxeda Highbank, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH 4/6] arm: Add dummy support for co-processor 15's secure config register, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v6 2/6] arm: make the number of GIC interrupts configurable, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v2 6/6] arm: Remove incorrect comment in arm_timer, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v5 1/6] Add xgmac ethernet model, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v7 0/6] arm: add support for Calxeda Highbank SoC, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v7 3/6] ahci: add support for non-PCI based controllers, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v7 6/6] arm: Remove incorrect comment in arm_timer, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v7 2/6] arm: make the number of GIC interrupts configurable, Mark Langsdorf, 2012/01/11
- Re: [Qemu-devel] [PATCH v7 2/6] arm: make the number of GIC interrupts configurable, Andreas Färber, 2012/01/10
- Re: [Qemu-devel] [PATCH v7 2/6] arm: make the number of GIC interrupts configurable, Peter Maydell, 2012/01/11
- [Qemu-devel] [PATCH v7 1/6] Add xgmac ethernet model, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v7 4/6] arm: Add dummy support for co-processor 15's secure config register, Mark Langsdorf, 2012/01/11