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Re: [Qemu-devel] [Android-virt] [PATCH 02/12] arm: make the number of GI
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [Android-virt] [PATCH 02/12] arm: make the number of GIC interrupts configurable |
Date: |
Fri, 27 Jan 2012 09:01:40 +0000 |
On 27 January 2012 00:33, Rusty Russell <address@hidden> wrote:
> Peter Maydell wrote:
>> Anyway, if we would otherwise die horribly later on we should
>> catch these cases, but it would be good to have at least a comment
>> saying that these are implementation limitations rather than
>> architectural ones.
>
> Good point. If we add an "supported" bit to each irq, we could do weird
> things, but presumably ->num_irq would still correspond to
> ITLinesNumber.
>
> I don't want to put too much of an essay in there. How's this:
>
> /* ITLinesNumber is represented as (N - 32) / 1. See
> gic_dist_readb. */
> if (s->num_irq < 32 || (s->num_irq % 32)) {
> hw_error("%u interrupt lines unsupported: not divisible by
> 32\n",
> num_irq);
I think that's a notch too terse for my taste. How about:
/* ITLinesNumber is represented as (N - 32) / 1 (see
* gic_dist_readb) so this is an implementation imposed
* restriction, not an architectural one:
*/
thanks
-- PMM
- [Qemu-devel] [PATCH 09/12] Add dummy implementation of generic timer cp15 registers, (continued)
[Qemu-devel] [PATCH 06/12] hw/vexpress.c: Factor out daughterboard-specific initialization, Peter Maydell, 2012/01/13
[Qemu-devel] [PATCH 03/12] hw/arm_boot.c: Make SMP boards specify address to poll in bootup loop, Peter Maydell, 2012/01/13
Re: [Qemu-devel] [PATCH 03/12] hw/arm_boot.c: Make SMP boards specify address to poll in bootup loop, andrzej zaborowski, 2012/01/16
[Qemu-devel] [PATCH 08/12] hw/a15mpcore.c: Add Cortex-A15 private peripheral model, Peter Maydell, 2012/01/13
[Qemu-devel] [PATCH 01/12] vexpress, realview: Add (dummy) L2 cache controller, Peter Maydell, 2012/01/13
[Qemu-devel] [PATCH 07/12] hw/vexpress.c: Instantiate the motherboard CLCD, Peter Maydell, 2012/01/13