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[Qemu-devel] [PATCH 10/60] AArch64: Add handling for br instructions
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PATCH 10/60] AArch64: Add handling for br instructions |
Date: |
Fri, 27 Sep 2013 02:48:04 +0200 |
This patch adds support for branch instructions that act on registers
rather than immediates (jmp, call, ret).
Signed-off-by: Alexander Graf <address@hidden>
---
target-arm/translate-a64.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 267fd4d..f4694b4 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -185,6 +185,29 @@ static void handle_b(DisasContext *s, uint32_t insn)
s->is_jmp = DISAS_TB_JUMP;
}
+static void handle_br(DisasContext *s, uint32_t insn)
+{
+ int branch_type = get_bits(insn, 21, 2);
+ int source = get_bits(insn, 5, 5);
+
+ switch (branch_type) {
+ case 0: /* JMP */
+ break;
+ case 1: /* CALL */
+ tcg_gen_movi_i64(cpu_reg(30), s->pc);
+ break;
+ case 2: /* RET */
+ source = 30;
+ break;
+ case 3:
+ unallocated_encoding(s);
+ return;
+ }
+
+ tcg_gen_mov_i64(cpu_pc, cpu_reg(source));
+ s->is_jmp = DISAS_JUMP;
+}
+
void disas_a64_insn(CPUARMState *env, DisasContext *s)
{
uint32_t insn;
@@ -199,6 +222,12 @@ void disas_a64_insn(CPUARMState *env, DisasContext *s)
case 0x5:
handle_b(s, insn);
goto insn_done;
+ case 0x35:
+ if ((insn & 0xff9ffc1f) == 0xd61f0000) {
+ handle_br(s, insn);
+ goto insn_done;
+ }
+ break;
}
switch ((insn >> 24) & 0x1f) {
--
1.7.12.4
- [Qemu-devel] [PATCH 00/60] AArch64 TCG emulation support, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 14/60] AArch64: Add orr instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 02/60] arm: Give the fpscr rounding modes names, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 01/60] arm: Use symbolic device names for vfp cmp, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 13/60] AArch64: Add stubs for a64 specific helpers, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 10/60] AArch64: Add handling for br instructions,
Alexander Graf <=
- [Qemu-devel] [PATCH 05/60] softfloat: Add stubs for int16 conversion, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 12/60] AArch64: Add ldarx style instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 09/60] AArch64: Add b and bl handling, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 08/60] AArch64: Add support to print VFP registers in CPU, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 22/60] AArch64: Add AdvSIMD scalar three same group handling, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 11/60] AArch64: Add STP instruction emulation, Alexander Graf, 2013/09/26