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Re: [Qemu-devel] [PATCH 14/21] target-arm: A64: Implement remaining inte
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-devel] [PATCH 14/21] target-arm: A64: Implement remaining integer scalar-3-same insns |
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Date: |
Tue, 28 Jan 2014 13:01:23 -0800 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 |
On 01/26/2014 11:25 AM, Peter Maydell wrote:
> Implement the remaining integer instructions in the scalar-three-reg-same
> group: SQADD, UQADD, SQSUB, UQSUB, SQSHL, UQSHL, SQRSHL, UQRSHL,
> SQDMULH, SQRDMULH.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> target-arm/translate-a64.c | 106
> +++++++++++++++++++++++++++++++++++++--------
> 1 file changed, 87 insertions(+), 19 deletions(-)
Reviewed-by: Richard Henderson <address@hidden>
r~
- [Qemu-devel] [PATCH 01/21] target-arm: A64: Add SIMD three-different multiply accumulate insns, (continued)
- [Qemu-devel] [PATCH 01/21] target-arm: A64: Add SIMD three-different multiply accumulate insns, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 21/21] target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 11/21] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 02/21] target-arm: A64: Add SIMD three-different ABDL instructions, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 05/21] target-arm: A64: Add logic ops from SIMD 3 same group, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 14/21] target-arm: A64: Implement remaining integer scalar-3-same insns, Peter Maydell, 2014/01/26
- Re: [Qemu-devel] [PATCH 14/21] target-arm: A64: Implement remaining integer scalar-3-same insns,
Richard Henderson <=
- [Qemu-devel] [PATCH 03/21] target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 04/21] target-arm: A64: Add top level decode for SIMD 3-same group, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 07/21] target-arm: A64: Add simple SIMD 3-same floating point ops, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 09/21] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 06/21] target-arm: A64: Add integer ops from SIMD 3-same group, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 08/21] target-arm: A64: Add SIMD shift by immediate, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 12/21] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 15/21] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc, Peter Maydell, 2014/01/26