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[Qemu-devel] [PULL 097/130] target-ppc: Altivec 2.07: Vector Logical Ins
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 097/130] target-ppc: Altivec 2.07: Vector Logical Instructions |
Date: |
Fri, 7 Mar 2014 00:33:44 +0100 |
From: Tom Musta <address@hidden>
This patch adds the Vector Logical Instructions that are introduced
in Power ISA Version 2.07: veqv, vnand and vorc.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/translate.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 75ab70b..ed1cf1d 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6852,6 +6852,9 @@ GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
+GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
+GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
+GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
#define GEN_VXFORM(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx)
\
@@ -10301,11 +10304,19 @@ GEN_VR_STVE(wx, 0x07, 0x06),
#undef GEN_VX_LOGICAL
#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
+
+#undef GEN_VX_LOGICAL_207
+#define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
+GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
+
GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
+GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
+GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
+GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
#undef GEN_VXFORM
#define GEN_VXFORM(name, opc2, opc3) \
--
1.8.1.4
- Re: [Qemu-devel] [PULL 073/130] Add Enhanced Three-Speed Ethernet Controller (eTSEC), (continued)
- [Qemu-devel] [PULL 088/130] target-ppc: Store Quadword, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 086/130] target-ppc: Add is_user_mode Utility Routine, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 087/130] target-ppc: Load Quadword, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 092/130] target-ppc: Altivec 2.07: Update AVR Structure, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 091/130] target-ppc: Altivec 2.07: Add Instruction Flag, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 095/130] target-ppc: Altivec 2.07: Add Opcode Macro for VX Form Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 090/130] target-ppc: Add Store Quadword Conditional, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 097/130] target-ppc: Altivec 2.07: Vector Logical Instructions,
Alexander Graf <=
- [Qemu-devel] [PULL 098/130] target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword Modulo, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 094/130] target-ppc: Altivec 2.07: Add Support for Dual Altivec Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 096/130] target-ppc: Altivec 2.07: Add Support for R-Form Dual Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 093/130] target-ppc: Altivec 2.07: Add GEN_VXFORM3, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 101/130] target-ppc: Altivec 2.07: vmuluw Instruction, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 104/130] target-ppc: Altivec 2.07: Vector Min/Max Doubleword Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 100/130] target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 099/130] target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 106/130] target-ppc: Altivec 2.07: Unpack Signed Word Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 102/130] target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes, Alexander Graf, 2014/03/06