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[Qemu-devel] [PATCH v6 35/37] target-arm: Make Cortex-A15 CBAR read-only
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v6 35/37] target-arm: Make Cortex-A15 CBAR read-only |
Date: |
Thu, 10 Apr 2014 17:15:34 +0100 |
The Cortex-A15's CBAR register is actually read-only (unlike that
of the Cortex-A9). Correct our model to match the hardware.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
target-arm/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index f9f6187..c0ddc3e 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -744,7 +744,7 @@ static void cortex_a15_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- set_feature(&cpu->env, ARM_FEATURE_CBAR);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
set_feature(&cpu->env, ARM_FEATURE_LPAE);
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
cpu->midr = 0x412fc0f1;
--
1.9.1
- Re: [Qemu-devel] [PATCH v6 18/37] target-arm: Move arm_log_exception() into internals.h, (continued)
- [Qemu-devel] [PATCH v6 24/37] target-arm: Implement AArch64 view of CONTEXTIDR, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 04/37] target-arm: Provide correct syndrome information for cpreg access traps, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 03/37] target-arm: Define exception record for AArch64 exceptions, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 05/37] target-arm: Add support for generating exceptions with syndrome information, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 06/37] target-arm: Provide syndrome information for MMU faults, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 17/37] target-arm: Implement AArch64 SPSR_EL1, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 35/37] target-arm: Make Cortex-A15 CBAR read-only,
Peter Maydell <=
- [Qemu-devel] [PATCH v6 22/37] hw/arm/virt: Add support for Cortex-A57, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 30/37] target-arm: Implement auxiliary fault status registers, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 36/37] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 21/37] target-arm: Add Cortex-A57 processor, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 23/37] target-arm: Implement AArch64 views of AArch32 ID registers, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 14/37] target-arm: Implement AArch64 views of fault status and data registers, Peter Maydell, 2014/04/10