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[Qemu-devel] [PATCH v6 22/37] hw/arm/virt: Add support for Cortex-A57
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v6 22/37] hw/arm/virt: Add support for Cortex-A57 |
Date: |
Thu, 10 Apr 2014 17:15:21 +0100 |
Support the Cortex-A57 in the virt machine model.
Signed-off-by: Peter Maydell <address@hidden>
---
This should perhaps not be just stealing the a15mpcore_priv
on the basis that it's a GICv2...
---
hw/arm/virt.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 2bbc931..e23868a 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -123,6 +123,14 @@ static VirtBoardInfo machines[] = {
.irqmap = a15irqmap,
},
{
+ .cpu_model = "cortex-a57",
+ /* Our A57 has an A15-style GICv2, so we can use a15mpcore_priv */
+ .qdevname = "a15mpcore_priv",
+ .gic_compatible = "arm,cortex-a15-gic",
+ .memmap = a15memmap,
+ .irqmap = a15irqmap,
+ },
+ {
.cpu_model = "host",
/* We use the A15 private peripheral model to get a V2 GIC */
.qdevname = "a15mpcore_priv",
--
1.9.1
- [Qemu-devel] [PATCH v6 24/37] target-arm: Implement AArch64 view of CONTEXTIDR, (continued)
- [Qemu-devel] [PATCH v6 24/37] target-arm: Implement AArch64 view of CONTEXTIDR, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 04/37] target-arm: Provide correct syndrome information for cpreg access traps, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 03/37] target-arm: Define exception record for AArch64 exceptions, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 05/37] target-arm: Add support for generating exceptions with syndrome information, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 06/37] target-arm: Provide syndrome information for MMU faults, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 17/37] target-arm: Implement AArch64 SPSR_EL1, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 35/37] target-arm: Make Cortex-A15 CBAR read-only, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 22/37] hw/arm/virt: Add support for Cortex-A57,
Peter Maydell <=
- [Qemu-devel] [PATCH v6 30/37] target-arm: Implement auxiliary fault status registers, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 36/37] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 21/37] target-arm: Add Cortex-A57 processor, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 23/37] target-arm: Implement AArch64 views of AArch32 ID registers, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 14/37] target-arm: Implement AArch64 views of fault status and data registers, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 31/37] target-arm: Implement AArch64 address translation operations, Peter Maydell, 2014/04/10