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[Qemu-devel] [PATCH 08/40] target-alpha: Convert opcode 0x14 to source/s
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 08/40] target-alpha: Convert opcode 0x14 to source/sink |
Date: |
Thu, 17 Apr 2014 12:32:43 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target-alpha/translate.c | 44 ++++++++++++++++++--------------------------
1 file changed, 18 insertions(+), 26 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 4a4876b..2afda77 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -206,7 +206,7 @@ static TCGv __attribute__((unused)) load_fpr(DisasContext
*ctx, unsigned reg)
}
}
-static TCGv __attribute__((unused)) dest_fpr(DisasContext *ctx, unsigned reg)
+static TCGv dest_fpr(DisasContext *ctx, unsigned reg)
{
if (likely(reg < 31)) {
return cpu_fir[reg];
@@ -1861,6 +1861,7 @@ static ExitStatus translate_one(DisasContext *ctx,
uint32_t insn)
uint8_t opc, ra, rb, rc, fpfn, fn7, lit;
bool islit;
TCGv va, vb, vc, tmp;
+ TCGv_i32 t32;
ExitStatus ret;
/* Decode all instruction fields */
@@ -2373,21 +2374,19 @@ static ExitStatus translate_one(DisasContext *ctx,
uint32_t insn)
goto invalid_opc;
}
break;
+
case 0x14:
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX);
switch (fpfn) { /* fn11 & 0x3F */
case 0x04:
/* ITOFS */
REQUIRE_REG_31(rb);
- if (likely(rc != 31)) {
- if (ra != 31) {
- TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]);
- gen_helper_memory_to_s(cpu_fir[rc], tmp);
- tcg_temp_free_i32(tmp);
- } else
- tcg_gen_movi_i64(cpu_fir[rc], 0);
- }
+ t32 = tcg_temp_new_i32();
+ va = load_gpr(ctx, ra);
+ vc = dest_fpr(ctx, rc);
+ tcg_gen_trunc_i64_i32(t32, va);
+ gen_helper_memory_to_s(vc, t32);
+ tcg_temp_free_i32(t32);
break;
case 0x0A:
/* SQRTF */
@@ -2402,26 +2401,19 @@ static ExitStatus translate_one(DisasContext *ctx,
uint32_t insn)
case 0x14:
/* ITOFF */
REQUIRE_REG_31(rb);
- if (likely(rc != 31)) {
- if (ra != 31) {
- TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]);
- gen_helper_memory_to_f(cpu_fir[rc], tmp);
- tcg_temp_free_i32(tmp);
- } else
- tcg_gen_movi_i64(cpu_fir[rc], 0);
- }
+ t32 = tcg_temp_new_i32();
+ va = load_gpr(ctx, ra);
+ vc = dest_fpr(ctx, rc);
+ tcg_gen_trunc_i64_i32(t32, va);
+ gen_helper_memory_to_f(vc, t32);
+ tcg_temp_free_i32(t32);
break;
case 0x24:
/* ITOFT */
REQUIRE_REG_31(rb);
- if (likely(rc != 31)) {
- if (ra != 31) {
- tcg_gen_mov_i64(cpu_fir[rc], cpu_ir[ra]);
- } else {
- tcg_gen_movi_i64(cpu_fir[rc], 0);
- }
- }
+ va = load_gpr(ctx, ra);
+ vc = dest_fpr(ctx, rc);
+ tcg_gen_mov_i64(vc, va);
break;
case 0x2A:
/* SQRTG */
--
1.9.0
- [Qemu-devel] [PATCH 00/40] target-alpha queue, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 03/40] target-alpha: Introduce REQUIRE_REG_31, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 05/40] target-alpha: Convert opcode 0x11 to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 04/40] target-alpha: Introduce functions for source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 06/40] target-alpha: Convert opcode 0x12 to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 02/40] target-alpha: Introduce REQUIRE_TB_FLAG, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 07/40] target-alpha: Convert opcode 0x13 to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 09/40] target-alpha: Convert opcode 0x17 to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 08/40] target-alpha: Convert opcode 0x14 to source/sink,
Richard Henderson <=
- [Qemu-devel] [PATCH 01/40] target-alpha: fix the braces, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 11/40] target-alpha: Convert opcode 0x1A to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 13/40] target-alpha: Convert opcode 0x1C to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 10/40] target-alpha: Convert opcode 0x18 to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 14/40] target-alpha: Convert opcode 0x1E to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 12/40] target-alpha: Convert opcode 0x1B to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 15/40] target-alpha: Convert opcode 0x1F to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 17/40] target-alpha: Convert gen_store_conditional to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 16/40] target-alpha: Convert gen_load/store_mem to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 18/40] target-alpha: Convert gen_cmp to source/sink, Richard Henderson, 2014/04/17