[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 13/40] target-alpha: Convert opcode 0x1C to source/s
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 13/40] target-alpha: Convert opcode 0x1C to source/sink |
Date: |
Thu, 17 Apr 2014 12:32:48 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target-alpha/translate.c | 73 +++++++++++++-----------------------------------
1 file changed, 19 insertions(+), 54 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 3a0cf6f..6664304 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2833,43 +2833,30 @@ static ExitStatus translate_one(DisasContext *ctx,
uint32_t insn)
#else
goto invalid_opc;
#endif
+
case 0x1C:
+ vc = dest_gpr(ctx, rc);
switch (fn7) {
case 0x00:
/* SEXTB */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX);
REQUIRE_REG_31(ra);
- if (likely(rc != 31)) {
- if (islit) {
- tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int8_t)lit));
- } else {
- tcg_gen_ext8s_i64(cpu_ir[rc], cpu_ir[rb]);
- }
- }
+ vb = load_gpr_lit(ctx, rb, lit, islit);
+ tcg_gen_ext8s_i64(vc, vb);
break;
case 0x01:
/* SEXTW */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX);
REQUIRE_REG_31(ra);
- if (likely(rc != 31)) {
- if (islit) {
- tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int16_t)lit));
- } else {
- tcg_gen_ext16s_i64(cpu_ir[rc], cpu_ir[rb]);
- }
- }
+ vb = load_gpr_lit(ctx, rb, lit, islit);
+ tcg_gen_ext16s_i64(vc, vb);
break;
case 0x30:
/* CTPOP */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX);
REQUIRE_REG_31(ra);
- if (likely(rc != 31)) {
- if (islit) {
- tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit));
- } else {
- gen_helper_ctpop(cpu_ir[rc], cpu_ir[rb]);
- }
- }
+ vb = load_gpr_lit(ctx, rb, lit, islit);
+ gen_helper_ctpop(vc, vb);
break;
case 0x31:
/* PERR */
@@ -2880,25 +2867,15 @@ static ExitStatus translate_one(DisasContext *ctx,
uint32_t insn)
/* CTLZ */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX);
REQUIRE_REG_31(ra);
- if (likely(rc != 31)) {
- if (islit) {
- tcg_gen_movi_i64(cpu_ir[rc], clz64(lit));
- } else {
- gen_helper_ctlz(cpu_ir[rc], cpu_ir[rb]);
- }
- }
+ vb = load_gpr_lit(ctx, rb, lit, islit);
+ gen_helper_ctlz(vc, vb);
break;
case 0x33:
/* CTTZ */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX);
REQUIRE_REG_31(ra);
- if (likely(rc != 31)) {
- if (islit) {
- tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit));
- } else {
- gen_helper_cttz(cpu_ir[rc], cpu_ir[rb]);
- }
- }
+ vb = load_gpr_lit(ctx, rb, lit, islit);
+ gen_helper_cttz(vc, vb);
break;
case 0x34:
/* UNPKBW */
@@ -2968,30 +2945,18 @@ static ExitStatus translate_one(DisasContext *ctx,
uint32_t insn)
/* FTOIT */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX);
REQUIRE_REG_31(rb);
- if (likely(rc != 31)) {
- if (ra != 31) {
- tcg_gen_mov_i64(cpu_ir[rc], cpu_fir[ra]);
- } else {
- tcg_gen_movi_i64(cpu_ir[rc], 0);
- }
- }
+ va = load_fpr(ctx, ra);
+ tcg_gen_mov_i64(vc, va);
break;
case 0x78:
/* FTOIS */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX);
REQUIRE_REG_31(rb);
- if (rc != 31) {
- TCGv_i32 tmp1 = tcg_temp_new_i32();
- if (ra != 31) {
- gen_helper_s_to_memory(tmp1, cpu_fir[ra]);
- } else {
- TCGv tmp2 = tcg_const_i64(0);
- gen_helper_s_to_memory(tmp1, tmp2);
- tcg_temp_free(tmp2);
- }
- tcg_gen_ext_i32_i64(cpu_ir[rc], tmp1);
- tcg_temp_free_i32(tmp1);
- }
+ t32 = tcg_temp_new_i32();
+ va = load_fpr(ctx, ra);
+ gen_helper_s_to_memory(t32, va);
+ tcg_gen_ext_i32_i64(vc, t32);
+ tcg_temp_free_i32(t32);
break;
default:
goto invalid_opc;
--
1.9.0
- [Qemu-devel] [PATCH 03/40] target-alpha: Introduce REQUIRE_REG_31, (continued)
- [Qemu-devel] [PATCH 03/40] target-alpha: Introduce REQUIRE_REG_31, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 05/40] target-alpha: Convert opcode 0x11 to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 04/40] target-alpha: Introduce functions for source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 06/40] target-alpha: Convert opcode 0x12 to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 02/40] target-alpha: Introduce REQUIRE_TB_FLAG, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 07/40] target-alpha: Convert opcode 0x13 to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 09/40] target-alpha: Convert opcode 0x17 to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 08/40] target-alpha: Convert opcode 0x14 to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 01/40] target-alpha: fix the braces, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 11/40] target-alpha: Convert opcode 0x1A to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 13/40] target-alpha: Convert opcode 0x1C to source/sink,
Richard Henderson <=
- [Qemu-devel] [PATCH 10/40] target-alpha: Convert opcode 0x18 to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 14/40] target-alpha: Convert opcode 0x1E to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 12/40] target-alpha: Convert opcode 0x1B to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 15/40] target-alpha: Convert opcode 0x1F to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 17/40] target-alpha: Convert gen_store_conditional to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 16/40] target-alpha: Convert gen_load/store_mem to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 18/40] target-alpha: Convert gen_cmp to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 19/40] target-alpha: Convert ARITH3_EX to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 20/40] target-alpha: Convert gen_cmov to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 22/40] target-alpha: Convert gen_ext_h/l to source/sink, Richard Henderson, 2014/04/17