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[Qemu-devel] [PULL 08/26] target-arm: Use a 1:1 mapping between EL and M
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 08/26] target-arm: Use a 1:1 mapping between EL and MMU index |
Date: |
Tue, 27 May 2014 17:28:16 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 8 ++++----
target-arm/translate.h | 6 +-----
2 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c83f249..5aa978d 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1080,12 +1080,12 @@ static inline CPUARMState *cpu_init(const char
*cpu_model)
#define cpu_list arm_cpu_list
/* MMU modes definitions */
-#define MMU_MODE0_SUFFIX _kernel
-#define MMU_MODE1_SUFFIX _user
-#define MMU_USER_IDX 1
+#define MMU_MODE0_SUFFIX _user
+#define MMU_MODE1_SUFFIX _kernel
+#define MMU_USER_IDX 0
static inline int cpu_mmu_index (CPUARMState *env)
{
- return arm_current_pl(env) ? 0 : 1;
+ return arm_current_pl(env);
}
#include "exec/cpu-all.h"
diff --git a/target-arm/translate.h b/target-arm/translate.h
index 8737af0..31a0104 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -54,11 +54,7 @@ static inline int arm_dc_feature(DisasContext *dc, int
feature)
static inline int get_mem_index(DisasContext *s)
{
-#ifdef CONFIG_USER_ONLY
- return 1;
-#else
- return s->user;
-#endif
+ return s->current_pl;
}
/* target-specific extra values for is_jmp */
--
1.9.2
- [Qemu-devel] [PULL 22/26] target-arm: A64: Generalize ERET to various ELs, (continued)
- [Qemu-devel] [PULL 22/26] target-arm: A64: Generalize ERET to various ELs, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 21/26] target-arm: A64: Trap ERET from EL0 at translation time, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 17/26] target-arm: Add a feature flag for EL3, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 18/26] target-arm: Register EL2 versions of ELR and SPSR, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 19/26] target-arm: Register EL3 versions of ELR and SPSR, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 16/26] target-arm: Add a feature flag for EL2, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 15/26] target-arm: A64: Introduce aarch64_banked_spsr_index(), Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 23/26] target-arm: A64: Generalize update_spsel for the various ELs, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 25/26] target-arm: A64: Register VBAR_EL2, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 14/26] target-arm: Add SPSR entries for EL2/HYP and EL3/MON, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 08/26] target-arm: Use a 1:1 mapping between EL and MMU index,
Peter Maydell <=
- [Qemu-devel] [PULL 13/26] target-arm: A64: Add ELR entries for EL2 and 3, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 20/26] target-arm: A64: Forbid ERET to higher or unimplemented ELs, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 05/26] target-arm/translate.c: Clean up mmu index handling for ldrt/strt, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 06/26] target-arm/translate.c: Use get_mem_index() for SRS memory accesses, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 02/26] hw/display/pxa2xx_lcd: Fix 16bpp+alpha and 18bpp+alpha palette formats, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 07/26] target-arm: A32: Use get_mem_index for load/stores, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 09/26] target-arm: Make elr_el1 an array, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 03/26] target-arm: implement CPACR register logic for ARMv7, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 04/26] target-arm: Move get_mem_index to translate.h, Peter Maydell, 2014/05/27
- Re: [Qemu-devel] [PULL 00/26] target-arm queue, Peter Maydell, 2014/05/28