[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 066/118] PPC: Fix SPR access control of L1CFG0
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 066/118] PPC: Fix SPR access control of L1CFG0 |
Date: |
Wed, 4 Jun 2014 14:44:07 +0200 |
The L1CFG0 register on e200 and e500 is "User RO" according to the
specifications. So let's make it user readable and world unwritable.
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/translate_init.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 1d64ec9..07f723d 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -4433,8 +4433,8 @@ static void init_proc_e200 (CPUPPCState *env)
0x00000000);
/* XXX : not implemented */
spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
@@ -4766,8 +4766,8 @@ static void init_proc_e500 (CPUPPCState *env, int version)
0x00000000);
/* XXX : not implemented */
spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
l1cfg0);
/* XXX : not implemented */
spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
--
1.8.1.4
- [Qemu-devel] [PULL 058/118] target-ppc: Refactor AES Instructions, (continued)
- [Qemu-devel] [PULL 058/118] target-ppc: Refactor AES Instructions, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 064/118] PPC: Make all e500 CPUs SVR aware, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Alexander Graf, 2014/06/04
- Re: [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Mark Cave-Ayland, 2014/06/20
- Re: [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, BALATON Zoltan, 2014/06/20
- Re: [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Mark Cave-Ayland, 2014/06/20
- Re: [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, BALATON Zoltan, 2014/06/20
- Re: [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Alexander Graf, 2014/06/23
- Re: [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, BALATON Zoltan, 2014/06/23
- Re: [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, BALATON Zoltan, 2014/06/23
[Qemu-devel] [PULL 066/118] PPC: Fix SPR access control of L1CFG0,
Alexander Graf <=
[Qemu-devel] [PULL 074/118] spapr: Add ibm, chip-id property in device tree, Alexander Graf, 2014/06/04
[Qemu-devel] [PULL 069/118] PPC: Add dcbtls emulation, Alexander Graf, 2014/06/04
[Qemu-devel] [PULL 073/118] spapr: Add support for time base offset migration, Alexander Graf, 2014/06/04
[Qemu-devel] [PULL 061/118] PPC: e500: implement PCI INTx routing, Alexander Graf, 2014/06/04
[Qemu-devel] [PULL 072/118] PPC: e500: Move to u-boot as firmware, Alexander Graf, 2014/06/04
[Qemu-devel] [PULL 068/118] PPC: Properly emulate L1CSR0 and L1CSR1, Alexander Graf, 2014/06/04
[Qemu-devel] [PULL 070/118] PPC: e500: Expose kernel load address in dt, Alexander Graf, 2014/06/04
[Qemu-devel] [PULL 071/118] PPC: Add u-boot firmware for e500, Alexander Graf, 2014/06/04
[Qemu-devel] [PULL 015/118] libdecnumber: Introduce libdecnumber Code, Alexander Graf, 2014/06/04
Re: [Qemu-devel] [PULL 00/118] ppc patch queue 2014-06-04, Peter Maydell, 2014/06/05