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[Qemu-devel] [PATCH 11/15] hw/intc/arm_gic: Change behavior of EOIR writ
From: |
Fabian Aggeler |
Subject: |
[Qemu-devel] [PATCH 11/15] hw/intc/arm_gic: Change behavior of EOIR writes |
Date: |
Fri, 22 Aug 2014 12:29:48 +0200 |
Grouping (GICv2) and Security Extensions change the behavior of EOIR
writes. Completing Group0 interrupts is only allowed from Secure state
and completing Group1 interrupts from Secure state is only allowed if
AckCtl bit is set.
Signed-off-by: Fabian Aggeler <address@hidden>
---
hw/intc/arm_gic.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 78efae1..a96f4a2 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -355,6 +355,21 @@ void gic_complete_irq(GICState *s, int cpu, int irq)
GIC_SET_PENDING(irq, cm);
update = 1;
}
+ } else if ((s->revision >= 2 && !s->security_extn)
+ || (s->security_extn && !ns_access())) {
+ /* Handle GICv2 without Security Extensions or GIC with Security
+ * Extensions and a secure write.
+ */
+ if (!GIC_TEST_GROUP0(irq, cm)
+ && !(s->cpu_control[cpu][0] & GICC_CTLR_S_ACK_CTL)) {
+ /* Unpredictable. We choose to ignore. */
+ DPRINTF("EOI for Group1 interrupt %d ignored "
+ "(AckCtl disabled)\n", irq);
+ return;
+ }
+ } else if (s->security_extn && ns_access() && GIC_TEST_GROUP0(irq, cm)) {
+ DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq);
+ return;
}
if (irq != s->running_irq[cpu]) {
--
1.8.3.2
- [Qemu-devel] [PATCH 00/15] target-arm: Add GICv1/SecExt and GICv2/Grouping, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 02/15] hw/arm/vexpress.c: Wire FIQ between CPU <> GIC, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 15/15] hw/intc/arm_gic: add gic_update() for grouping, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 10/15] hw/intc/arm_gic: Handle grouping for GICC_HPPIR, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 04/15] hw/intc/arm_gic: Add ns_access() function, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 05/15] hw/intc/arm_gic: Add Interrupt Group Registers, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 06/15] hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 08/15] hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 12/15] hw/intc/arm_gic: Change behavior of IAR writes, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 11/15] hw/intc/arm_gic: Change behavior of EOIR writes,
Fabian Aggeler <=
- [Qemu-devel] [PATCH 01/15] hw/intc/arm_gic: Request FIQ sources, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 07/15] hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 03/15] hw/intc/arm_gic: Add Security Extensions property, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 09/15] hw/intc/arm_gic: Implement Non-secure view of RPR, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 13/15] hw/intc/arm_gic: Restrict priority view, Fabian Aggeler, 2014/08/22