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[Qemu-devel] [PULL 12/19] target-arm: Break out exception masking to a s
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/19] target-arm: Break out exception masking to a separate func |
Date: |
Mon, 29 Sep 2014 19:26:46 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
[PMM: updated to account for recent cpu-exec refactoring]
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.c | 7 ++-----
target-arm/cpu.h | 15 +++++++++++++++
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 248778d..b7cdcd7 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -187,12 +187,10 @@ static void arm_cpu_reset(CPUState *s)
bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
bool ret = false;
if (interrupt_request & CPU_INTERRUPT_FIQ
- && !(env->daif & PSTATE_F)) {
+ && arm_excp_unmasked(cs, EXCP_FIQ)) {
cs->exception_index = EXCP_FIQ;
cc->do_interrupt(cs);
ret = true;
@@ -207,8 +205,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
We avoid this by disabling interrupts when
pc contains a magic address. */
if (interrupt_request & CPU_INTERRUPT_HARD
- && !(env->daif & PSTATE_I)
- && (!IS_M(env) || env->regs[15] < 0xfffffff0)) {
+ && arm_excp_unmasked(cs, EXCP_IRQ)) {
cs->exception_index = EXCP_IRQ;
cc->do_interrupt(cs);
ret = true;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index a3ba624..cc2c210 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1172,6 +1172,21 @@ bool write_cpustate_to_list(ARMCPU *cpu);
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
+static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx)
+{
+ CPUARMState *env = cs->env_ptr;
+
+ switch (excp_idx) {
+ case EXCP_FIQ:
+ return !(env->daif & PSTATE_F);
+ case EXCP_IRQ:
+ return !(env->daif & PSTATE_I)
+ && (!IS_M(env) || env->regs[15] < 0xfffffff0);
+ default:
+ g_assert_not_reached();
+ }
+}
+
static inline CPUARMState *cpu_init(const char *cpu_model)
{
ARMCPU *cpu = cpu_arm_init(cpu_model);
--
1.9.1
- [Qemu-devel] [PULL 00/19] target-arm queue, Peter Maydell, 2014/09/29
- [Qemu-devel] [PULL 18/19] target-arm: Add IRQ and FIQ routing to EL2 and 3, Peter Maydell, 2014/09/29
- [Qemu-devel] [PULL 17/19] target-arm: A64: Emulate the SMC insn, Peter Maydell, 2014/09/29
- [Qemu-devel] [PULL 15/19] target-arm: A64: Emulate the HVC insn, Peter Maydell, 2014/09/29
- [Qemu-devel] [PULL 12/19] target-arm: Break out exception masking to a separate func,
Peter Maydell <=
- [Qemu-devel] [PULL 07/19] hw/input/tsc210x.c: Delete unused array tsc2101_rates, Peter Maydell, 2014/09/29
- [Qemu-devel] [PULL 06/19] hw/display/pxa2xx_lcd.c: Remove unused function pxa2xx_dma_rdst_set, Peter Maydell, 2014/09/29
- [Qemu-devel] [PULL 04/19] hw/display/blizzard.c: Delete unused function blizzard_rgb2yuv, Peter Maydell, 2014/09/29
- [Qemu-devel] [PULL 19/19] target-arm: Add support for VIRQ and VFIQ, Peter Maydell, 2014/09/29
- [Qemu-devel] [PULL 03/19] configure: Build GDB XML for 32 bit ARM CPUs into qemu aarch64 binaries, Peter Maydell, 2014/09/29
- [Qemu-devel] [PULL 05/19] hw/intc/imx_avic.c: Remove unused function imx_avic_set_prio(), Peter Maydell, 2014/09/29
- [Qemu-devel] [PULL 16/19] target-arm: Add a Hypervisor Trap exception type, Peter Maydell, 2014/09/29
- [Qemu-devel] [PULL 08/19] target-arm: Don't handle c15_cpar changes via tb_flush(), Peter Maydell, 2014/09/29
- [Qemu-devel] [PULL 14/19] target-arm: A64: Correct updates to FAR and ESR on exceptions, Peter Maydell, 2014/09/29
- [Qemu-devel] [PULL 13/19] target-arm: Don't take interrupts targeting lower ELs, Peter Maydell, 2014/09/29