[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v8 17/27] target-arm: add TCR_EL3 and make TTBCR
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v8 17/27] target-arm: add TCR_EL3 and make TTBCR banked |
Date: |
Fri, 31 Oct 2014 15:07:18 +0000 |
On 30 October 2014 21:28, Greg Bellows <address@hidden> wrote:
> From: Fabian Aggeler <address@hidden>
>
> Adds TCR_EL3 system register and makes existing TTBCR banked. Adjust
> translation functions to use TCR/TTBCR instance depending on CPU state.
>
> Signed-off-by: Fabian Aggeler <address@hidden>
> Signed-off-by: Greg Bellows <address@hidden>
>
> ---
>
> v5 -> v6
> - Changed _el field variants to be array based
>
> v4 -> v5
> - Changed c2_mask updates to use the TTBCR cpreg bank flag for selcting the
> secure bank instead of the A32_BANKED_CURRENT macro. This more accurately
> chooses the correct bank matching that of the TTBCR being accessed.
> ---
> target-arm/cpu.h | 10 +++++++++-
> target-arm/helper.c | 48 +++++++++++++++++++++++++++++++++++-------------
> target-arm/internals.h | 2 +-
> 3 files changed, 45 insertions(+), 15 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index fe96869..f125bdd 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -217,7 +217,15 @@ typedef struct CPUARMState {
> };
> uint64_t ttbr1_el[4];
> };
> - uint64_t c2_control; /* MMU translation table base control. */
> + union { /* MMU translation table base control. */
> + struct {
> + uint64_t _unused_ttbcr_0;
> + uint64_t ttbcr_ns;
> + uint64_t _unused_ttbcr_1;
> + uint64_t ttbcr_s;
> + };
> + uint64_t tcr_el[4];
> + };
> uint32_t c2_mask; /* MMU translation table base selection mask. */
> uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
> uint32_t c2_data; /* MPU data cachable bits. */
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 598f0d1..896b40d 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1659,11 +1659,12 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
> .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
> .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
> .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
> - .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
> + .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
> { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
> .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn =
> vmsa_ttbcr_write,
> .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
> - .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
> + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ttbcr_s),
> + offsetoflow32(CPUARMState, cp15.ttbcr_ns) } },
> /* 64-bit FAR; this entry also gives us the AArch32 DFAR */
> { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH,
> .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
> @@ -2349,6 +2350,11 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
> .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 6, .opc2 = 0,
> .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
> .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
> + { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 6, .opc2 = 2,
> + .access = PL3_RW, .writefn = vmsa_tcr_el1_write,
> + .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
> + .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
> { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
> .type = ARM_CP_NO_MIGRATE,
> .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
> @@ -4435,13 +4441,13 @@ static bool get_level1_table_address(CPUARMState
> *env, uint32_t *table,
> * table registers.
> */
> if (address & env->cp15.c2_mask) {
> - if ((env->cp15.c2_control & TTBCR_PD1)) {
> + if (A32_BANKED_CURRENT_REG_GET(env, ttbcr) & TTBCR_PD1) {
> /* Translation table walk disabled for TTBR1 */
> return false;
> }
> *table = A32_BANKED_CURRENT_REG_GET(env, ttbr1) & 0xffffc000;
> } else {
> - if ((env->cp15.c2_control & TTBCR_PD0)) {
> + if (A32_BANKED_CURRENT_REG_GET(env, ttbcr) & TTBCR_PD0) {
> /* Translation table walk disabled for TTBR0 */
> return false;
> }
> @@ -4701,13 +4707,29 @@ static int get_phys_addr_lpae(CPUARMState *env,
> target_ulong address,
> int32_t va_size = 32;
> int32_t tbi = 0;
> uint32_t cur_el = arm_current_el(env);
> + uint64_t tcr;
>
> - if (arm_el_is_aa64(env, 1)) {
> + if (arm_el_is_aa64(env, 3)) {
> + switch (cur_el) {
> + case 3:
> + tcr = env->cp15.tcr_el[3];
> + break;
> + case 1:
> + case 0:
> + default:
> + tcr = env->cp15.tcr_el[1];
> + }
> +
> + } else {
> + tcr = A32_BANKED_CURRENT_REG_GET(env, ttbcr);
> + }
Again, I would pull out the TCR_EL3 definition and attempts
at handling the 64 bit EL3 into their own patch and stick
them on the shelf for later.
thanks
-- PMM
- Re: [Qemu-devel] [PATCH v8 19/27] target-arm: make DACR banked, (continued)
- [Qemu-devel] [PATCH v8 18/27] target-arm: make c2_mask and c2_base_mask banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 16/27] target-arm: add TTBR0_EL3 and make TTBR0/1 banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 21/27] target-arm: make DFSR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 24/27] target-arm: make VBAR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 17/27] target-arm: add TCR_EL3 and make TTBCR banked, Greg Bellows, 2014/10/31
- Re: [Qemu-devel] [PATCH v8 17/27] target-arm: add TCR_EL3 and make TTBCR banked,
Peter Maydell <=
- [Qemu-devel] [PATCH v8 05/27] target-arm: add CPREG secure state support, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 01/27] target-arm: extend async excp masking, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 04/27] target-arm: add non-secure Translation Block flag, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 25/27] target-arm: make c13 cp regs banked (FCSEIDR, ...), Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 12/27] target-arm: add MVBAR support, Greg Bellows, 2014/10/31