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[Qemu-devel] [RFC 11/14] Print bbvec stats on 'magic' exceptions
From: |
Christopher Covington |
Subject: |
[Qemu-devel] [RFC 11/14] Print bbvec stats on 'magic' exceptions |
Date: |
Wed, 5 Aug 2015 12:51:20 -0400 |
This is necessary because we need a way to differentiate between
instructions executed in a PID by the benchmark we care about and those
executed by CRIU.
Written by Aaron Lindsay.
Signed-off-by: Christopher Covington <address@hidden>
---
bbv_profiler.c | 15 +++++++++++++++
bbv_profiler.h | 1 +
target-arm/helper-a64.c | 10 ++++++++++
target-arm/helper.c | 12 ++++++++++++
4 files changed, 38 insertions(+)
diff --git a/bbv_profiler.c b/bbv_profiler.c
index 51e8060..66984b2 100644
--- a/bbv_profiler.c
+++ b/bbv_profiler.c
@@ -19,6 +19,12 @@
#include <assert.h>
#include "bbv_profiler.h"
+/* Magic number, which is set as bits 16-31 of the target of a branch which
+ * causes an exception to send a signal to the plugin.
+ */
+#define BBV_MAGIC_NUM 0xdead
+#define BBV_PRINT_STATS 0x0
+
static BasicBlockTraceHandle trace = NULL;
static uint32_t mode = 0;
static uint64_t pid = 0;
@@ -75,3 +81,12 @@ void bb_context_check_pid(uint64_t IC, uint64_t new_pid)
bbvec_pid_change(trace, new_pid, IC);
}
}
+
+/* Check if the bbv plugin is being signaled to do something by an exception */
+void bb_check_exception(uint64_t pc) {
+ if (((pc >> 16) & 0xffff) == BBV_MAGIC_NUM) {
+ uint16_t value = pc & 0xffff;
+ if (value == BBV_PRINT_STATS)
+ bbvec_print_stats(trace);
+ }
+}
diff --git a/bbv_profiler.h b/bbv_profiler.h
index 26dfa1f..b922451 100644
--- a/bbv_profiler.h
+++ b/bbv_profiler.h
@@ -31,5 +31,6 @@ int bbtrace_initialized(void);
void bb_process(uint64_t PC, uint64_t IC);
void bb_context_check_mode(uint64_t IC, uint32_t mode);
void bb_context_check_pid(uint64_t IC, uint64_t tpid);
+void bb_check_exception(uint64_t pc);
#endif
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index e647b90..95eb096 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -27,6 +27,10 @@
#include "qemu/crc32c.h"
#include <zlib.h> /* For crc32 */
+#ifdef CONFIG_BBVEC
+#include "bbv_profiler.h"
+#endif // CONFIG_BBVEC
+
/* C2.4.7 Multiply and divide */
/* special cases for 0 and LLONG_MIN are mandated by the standard */
uint64_t HELPER(udiv64)(uint64_t num, uint64_t den)
@@ -470,6 +474,12 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
uint64_t mask;
#endif
+#ifdef CONFIG_BBVEC
+ if (bbtrace_initialized()) {
+ bb_check_exception(is_a64(env) ? env->pc : env->regs[15]);
+ }
+#endif
+
uint32_t syndrome =
cs->exception_index == EXCP_ARMV8_HLT ?
env->exception.syndrome & ~0xffff :
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c1f4c47..297eb7c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4773,6 +4773,12 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
arm_log_exception(cs->exception_index);
+#ifdef CONFIG_BBVEC
+ if (bbtrace_initialized()) {
+ bb_check_exception(env->regs[15]);
+ }
+#endif
+
lr = 0xfffffff1;
if (env->v7m.current_sp)
lr |= 4;
@@ -5074,6 +5080,12 @@ void arm_cpu_do_interrupt(CPUState *cs)
return;
}
+#ifdef CONFIG_BBVEC
+ if (bbtrace_initialized()) {
+ bb_check_exception(env->regs[15]);
+ }
+#endif
+
/* If this is a debug exception we must update the DBGDSCR.MOE bits */
switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
case EC_BREAKPOINT:
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
- [Qemu-devel] [RFC 03/14] Fix makefile, (continued)
- [Qemu-devel] [RFC 03/14] Fix makefile, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 04/14] Modify load exclusive/store exclusive to use physical addresses with the monitor, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 02/14] Added semihosting support for A64 in full-system mode, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 05/14] Fixed TLB invalidate ops., Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 12/14] bbvec: Detect mode changes after uncached_cpsr update, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 10/14] bbvec: Move mode/PID change detection to register writes, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 07/14] Add PMU to ARM virt platform, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 08/14] Add instruction-counting infrastructure to target-arm, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 13/14] Enable negative icount values for QEMU., Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 11/14] Print bbvec stats on 'magic' exceptions,
Christopher Covington <=
- [Qemu-devel] [RFC 09/14] Implement remaining PMU functionality, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 06/14] Added support for block profiling for AArch32 and Aarch64, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 14/14] bbvec: Properly detect conditional thumb2 branching instructions, Christopher Covington, 2015/08/05
- Re: [Qemu-devel] RFC: ARM Semihosting, PMU, and BBV Changes, Peter Maydell, 2015/08/11