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[Qemu-devel] [PATCH v15 16/33] target-tilegx: Handle most bit manipulati
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v15 16/33] target-tilegx: Handle most bit manipulation instructions |
Date: |
Wed, 2 Sep 2015 18:31:08 -0700 |
The crc instructions are omitted from this set.
Signed-off-by: Richard Henderson <address@hidden>
---
target-tilegx/helper.c | 23 ++++++++++++++++
target-tilegx/helper.h | 2 ++
target-tilegx/translate.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 92 insertions(+), 1 deletion(-)
diff --git a/target-tilegx/helper.c b/target-tilegx/helper.c
index 5b37a8c..9a73edc 100644
--- a/target-tilegx/helper.c
+++ b/target-tilegx/helper.c
@@ -40,6 +40,29 @@ uint64_t helper_cnttz(uint64_t arg)
return ctz64(arg);
}
+uint64_t helper_pcnt(uint64_t arg)
+{
+ return ctpop64(arg);
+}
+
+uint64_t helper_revbits(uint64_t arg)
+{
+ /* Assign the correct byte position. */
+ arg = bswap64(arg);
+
+ /* Assign the correct nibble position. */
+ arg = ((arg & 0xf0f0f0f0f0f0f0f0ULL) >> 4)
+ | ((arg & 0x0f0f0f0f0f0f0f0fULL) << 4);
+
+ /* Assign the correct bit position. */
+ arg = ((arg & 0x8888888888888888ULL) >> 3)
+ | ((arg & 0x4444444444444444ULL) >> 1)
+ | ((arg & 0x2222222222222222ULL) << 1)
+ | ((arg & 0x1111111111111111ULL) << 3);
+
+ return arg;
+}
+
/*
* Functional Description
* uint64_t a = rf[SrcA];
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index fd5517e..644d313 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -1,4 +1,6 @@
DEF_HELPER_2(exception, noreturn, env, i32)
DEF_HELPER_FLAGS_1(cntlz, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(cnttz, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_1(pcnt, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_1(revbits, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index c3f395f..d68ec13 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -177,6 +177,43 @@ static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv
tsrcb,
tcg_temp_free(t0);
}
+/* Shift the 128-bit value TSRCA:TSRCD riht by the number of bytes
+ specified by the bottom 3 bits of TSRCB, and set TDEST to the
+ low 64 bits of the resulting value. */
+static void gen_dblalign(TCGv tdest, TCGv tsrcd, TCGv tsrca, TCGv tsrcb)
+{
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_andi_tl(t0, tsrcb, 7);
+ tcg_gen_shli_tl(t0, t0, 3);
+ tcg_gen_shr_tl(tdest, tsrcd, t0);
+
+ /* We want to do "t0 = tsrca << (64 - t0)". Two's complement
+ arithmetic on a 6-bit field tells us that 64 - t0 is equal
+ to (t0 ^ 63) + 1. So we can do the shift in two parts,
+ neither of which will be an invalid shift by 64. */
+ tcg_gen_xori_tl(t0, t0, 63);
+ tcg_gen_shl_tl(t0, tsrca, t0);
+ tcg_gen_shli_tl(t0, t0, 1);
+ tcg_gen_or_tl(tdest, tdest, t0);
+
+ tcg_temp_free(t0);
+}
+
+/* Similarly, except that the 128-bit value is TSRCA:TSRCB, and the
+ right shift is an immediate. */
+static void gen_dblaligni(TCGv tdest, TCGv tsrca, TCGv tsrcb, int shr)
+{
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_shri_tl(t0, tsrcb, shr);
+ tcg_gen_shli_tl(tdest, tsrca, 64 - shr);
+ tcg_gen_or_tl(tdest, tdest, t0);
+
+ tcg_temp_free(t0);
+}
+
+
static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
unsigned dest, unsigned srca)
{
@@ -210,8 +247,14 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
switch (opext) {
case OE_RR_X0(CNTLZ):
case OE_RR_Y0(CNTLZ):
+ gen_helper_cntlz(tdest, tsrca);
+ mnemonic = "cntlz";
+ break;
case OE_RR_X0(CNTTZ):
case OE_RR_Y0(CNTTZ):
+ gen_helper_cnttz(tdest, tsrca);
+ mnemonic = "cnttz";
+ break;
case OE_RR_X1(DRAIN):
case OE_RR_X1(DTLBPR):
case OE_RR_X1(FINV):
@@ -251,11 +294,17 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
case OE_RR_Y1(LNK):
case OE_RR_X1(MF):
case OE_RR_X1(NAP):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RR_X0(PCNT):
case OE_RR_Y0(PCNT):
+ gen_helper_pcnt(tdest, tsrca);
+ mnemonic = "pcnt";
+ break;
case OE_RR_X0(REVBITS):
case OE_RR_Y0(REVBITS):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ gen_helper_revbits(tdest, tsrca);
+ mnemonic = "revbits";
+ break;
case OE_RR_X0(REVBYTES):
case OE_RR_Y0(REVBYTES):
tcg_gen_bswap64_tl(tdest, tsrca);
@@ -358,13 +407,26 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned
opext,
case OE_RRR(CMUL, 0, X0):
case OE_RRR(CRC32_32, 0, X0):
case OE_RRR(CRC32_8, 0, X0):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(DBLALIGN2, 0, X0):
case OE_RRR(DBLALIGN2, 0, X1):
+ gen_dblaligni(tdest, tsrca, tsrcb, 16);
+ mnemonic = "dblalign2";
+ break;
case OE_RRR(DBLALIGN4, 0, X0):
case OE_RRR(DBLALIGN4, 0, X1):
+ gen_dblaligni(tdest, tsrca, tsrcb, 32);
+ mnemonic = "dblalign4";
+ break;
case OE_RRR(DBLALIGN6, 0, X0):
case OE_RRR(DBLALIGN6, 0, X1):
+ gen_dblaligni(tdest, tsrca, tsrcb, 48);
+ mnemonic = "dblalign6";
+ break;
case OE_RRR(DBLALIGN, 0, X0):
+ gen_dblalign(tdest, load_gr(dc, dest), tsrca, tsrcb);
+ mnemonic = "dblalign";
+ break;
case OE_RRR(EXCH4, 0, X1):
case OE_RRR(EXCH, 0, X1):
case OE_RRR(FDOUBLE_ADDSUB, 0, X0):
@@ -516,7 +578,11 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned
opext,
case OE_RRR(SHRU, 0, X1):
case OE_RRR(SHRU, 6, Y0):
case OE_RRR(SHRU, 6, Y1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(SHUFFLEBYTES, 0, X0):
+ gen_helper_shufflebytes(tdest, load_gr(dc, dest), tsrca, tsrca);
+ mnemonic = "shufflebytes";
+ break;
case OE_RRR(ST1, 0, X1):
case OE_RRR(ST2, 0, X1):
case OE_RRR(ST4, 0, X1):
--
2.4.3
- [Qemu-devel] [PATCH v15 07/33] target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1, (continued)
- [Qemu-devel] [PATCH v15 07/33] target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 05/33] target-tilegx: Modify opcode_tilegx.h to fit QEMU usage, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 08/33] target-tilegx: Add special register information from Tilera Corporation, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 04/33] target-tilegx: Add opcode basic implementation from Tilera Corporation, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 09/33] target-tilegx: Add cpu basic features for linux-user, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 13/33] target-tilegx: Add TILE-Gx building files, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 10/33] target-tilegx: Add several helpers for instructions translation, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 14/33] target-tilegx: Handle simple logical operations, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 12/33] target-tilegx: Generate SEGV properly, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 16/33] target-tilegx: Handle most bit manipulation instructions,
Richard Henderson <=
- [Qemu-devel] [PATCH v15 15/33] target-tilegx: Handle arithmetic instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 17/33] target-tilegx: Handle basic load and store instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 11/33] target-tilegx: Framework for decoding bundles, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 18/33] target-tilegx: Handle post-increment load and store instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 19/33] target-tilegx: Handle unconditional jump instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 20/33] target-tilegx: Handle conditional branch instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 25/33] target-tilegx: Handle conditional move instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 21/33] target-tilegx: Handle comparison instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 22/33] target-tilegx: Implement system and memory management instructions, Richard Henderson, 2015/09/02