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[Qemu-devel] [PATCH v15 21/33] target-tilegx: Handle comparison instruct
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v15 21/33] target-tilegx: Handle comparison instructions |
Date: |
Wed, 2 Sep 2015 18:31:13 -0700 |
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-tilegx/translate.c | 39 +++++++++++++++++++++++++++++++++------
1 file changed, 33 insertions(+), 6 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 5d7aefa..0fbd11b 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -473,32 +473,52 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned
opext,
case OE_RRR(CMOVEQZ, 4, Y0):
case OE_RRR(CMOVNEZ, 0, X0):
case OE_RRR(CMOVNEZ, 4, Y0):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(CMPEQ, 0, X0):
case OE_RRR(CMPEQ, 0, X1):
case OE_RRR(CMPEQ, 3, Y0):
case OE_RRR(CMPEQ, 3, Y1):
+ tcg_gen_setcond_tl(TCG_COND_EQ, tdest, tsrca, tsrcb);
+ mnemonic = "cmpeq";
+ break;
case OE_RRR(CMPEXCH4, 0, X1):
case OE_RRR(CMPEXCH, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(CMPLES, 0, X0):
case OE_RRR(CMPLES, 0, X1):
case OE_RRR(CMPLES, 2, Y0):
case OE_RRR(CMPLES, 2, Y1):
+ tcg_gen_setcond_tl(TCG_COND_LE, tdest, tsrca, tsrcb);
+ mnemonic = "cmples";
+ break;
case OE_RRR(CMPLEU, 0, X0):
case OE_RRR(CMPLEU, 0, X1):
case OE_RRR(CMPLEU, 2, Y0):
case OE_RRR(CMPLEU, 2, Y1):
+ tcg_gen_setcond_tl(TCG_COND_LEU, tdest, tsrca, tsrcb);
+ mnemonic = "cmpleu";
+ break;
case OE_RRR(CMPLTS, 0, X0):
case OE_RRR(CMPLTS, 0, X1):
case OE_RRR(CMPLTS, 2, Y0):
case OE_RRR(CMPLTS, 2, Y1):
+ tcg_gen_setcond_tl(TCG_COND_LT, tdest, tsrca, tsrcb);
+ mnemonic = "cmplts";
+ break;
case OE_RRR(CMPLTU, 0, X0):
case OE_RRR(CMPLTU, 0, X1):
case OE_RRR(CMPLTU, 2, Y0):
case OE_RRR(CMPLTU, 2, Y1):
+ tcg_gen_setcond_tl(TCG_COND_LTU, tdest, tsrca, tsrcb);
+ mnemonic = "cmpltu";
+ break;
case OE_RRR(CMPNE, 0, X0):
case OE_RRR(CMPNE, 0, X1):
case OE_RRR(CMPNE, 3, Y0):
case OE_RRR(CMPNE, 3, Y1):
+ tcg_gen_setcond_tl(TCG_COND_NE, tdest, tsrca, tsrcb);
+ mnemonic = "cmpne";
+ break;
case OE_RRR(CMULAF, 0, X0):
case OE_RRR(CMULA, 0, X0):
case OE_RRR(CMULFR, 0, X0):
@@ -886,13 +906,25 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned
opext,
tcg_gen_andi_tl(tdest, tsrca, imm);
mnemonic = "andi";
break;
+ case OE(CMPEQI_OPCODE_Y0, 0, Y0):
+ case OE(CMPEQI_OPCODE_Y1, 0, Y1):
case OE_IM(CMPEQI, X0):
case OE_IM(CMPEQI, X1):
+ tcg_gen_setcondi_tl(TCG_COND_EQ, tdest, tsrca, imm);
+ mnemonic = "cmpeqi";
+ break;
+ case OE(CMPLTSI_OPCODE_Y0, 0, Y0):
+ case OE(CMPLTSI_OPCODE_Y1, 0, Y1):
case OE_IM(CMPLTSI, X0):
case OE_IM(CMPLTSI, X1):
+ tcg_gen_setcondi_tl(TCG_COND_LT, tdest, tsrca, imm);
+ mnemonic = "cmpltsi";
+ break;
case OE_IM(CMPLTUI, X0):
case OE_IM(CMPLTUI, X1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ tcg_gen_setcondi_tl(TCG_COND_LTU, tdest, tsrca, imm);
+ mnemonic = "cmpltui";
+ break;
case OE_IM(LD1S_ADD, X1):
memop = MO_SB;
mnemonic = "ld1s_add";
@@ -1042,11 +1074,6 @@ static TileExcp gen_rri_opcode(DisasContext *dc,
unsigned opext,
tcg_gen_ext32s_tl(tdest, tdest);
mnemonic = "addxli";
break;
- case OE(CMPEQI_OPCODE_Y0, 0, Y0):
- case OE(CMPEQI_OPCODE_Y1, 0, Y1):
- case OE(CMPLTSI_OPCODE_Y0, 0, Y0):
- case OE(CMPLTSI_OPCODE_Y1, 0, Y1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE(SHL16INSLI_OPCODE_X0, 0, X0):
case OE(SHL16INSLI_OPCODE_X1, 0, X1):
tcg_gen_shli_tl(tdest, tsrca, 16);
--
2.4.3
- [Qemu-devel] [PATCH v15 12/33] target-tilegx: Generate SEGV properly, (continued)
- [Qemu-devel] [PATCH v15 12/33] target-tilegx: Generate SEGV properly, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 16/33] target-tilegx: Handle most bit manipulation instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 15/33] target-tilegx: Handle arithmetic instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 17/33] target-tilegx: Handle basic load and store instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 11/33] target-tilegx: Framework for decoding bundles, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 18/33] target-tilegx: Handle post-increment load and store instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 19/33] target-tilegx: Handle unconditional jump instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 20/33] target-tilegx: Handle conditional branch instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 25/33] target-tilegx: Handle conditional move instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 21/33] target-tilegx: Handle comparison instructions,
Richard Henderson <=
- [Qemu-devel] [PATCH v15 22/33] target-tilegx: Implement system and memory management instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 24/33] target-tilegx: Handle shift instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 23/33] target-tilegx: Handle bitfield instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 26/33] target-tilegx: Handle scalar multiply instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 27/33] target-tilegx: Handle mask instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 29/33] target-tilegx: Handle mtspr, mfspr, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 28/33] target-tilegx: Handle v1cmpeq, v1cmpne, Richard Henderson, 2015/09/02