Re: [Qemu-devel] [PATCH v3 1/9] target-arm: Add HPFAR_EL2

[Peter Maydell]

On 7 October 2015 at 12:51, Alex Bennée <address@hidden> wrote:
>
> Edgar E. Iglesias <address@hidden> writes:
>
>> From: "Edgar E. Iglesias" <address@hidden>
>>
>> Signed-off-by: Edgar E. Iglesias <address@hidden>
>> ---
>>  target-arm/cpu.h    |  1 +
>>  target-arm/helper.c | 12 ++++++++++++
>>  2 files changed, 13 insertions(+)
>>
>> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
>> index cc1578c..895f2c2 100644
>> --- a/target-arm/cpu.h
>> +++ b/target-arm/cpu.h
>> @@ -278,6 +278,7 @@ typedef struct CPUARMState {
>>              };
>>              uint64_t far_el[4];
>>          };
>> +        uint64_t hpfar_el2;
>>          union { /* Translation result. */
>>              struct {
>>                  uint64_t _unused_par_0;
>> diff --git a/target-arm/helper.c b/target-arm/helper.c
>> index 8367997..5a5e5f0 100644
>> --- a/target-arm/helper.c
>> +++ b/target-arm/helper.c
>> @@ -3223,6 +3223,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
>>      { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
>>        .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
>>        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
>> +    { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
>> +      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
>> +      .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
>> +      .type = ARM_CP_CONST, .resetvalue = 0 },
>
> So what happens if access_el3_aa32ns_aa64any thinks it is OK to access
> the register from EL3 when there is no EL2? What ensures we get RES0?

...the fact we've defined it as an RW CONST register with a resetvalue
of zero? Or am I misunderstanding your question?

thanks
-- PMM