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[Qemu-devel] [PATCH v2 2/8] target-arm: Add computation of starting leve
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v2 2/8] target-arm: Add computation of starting level for S2 PTW |
Date: |
Thu, 1 Oct 2015 17:49:22 -0700 |
From: "Edgar E. Iglesias" <address@hidden>
The starting level for S2 pagetable walks is computed
differently from the S1 starting level. Implement the S2
variant.
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/helper.c | 35 +++++++++++++++++++++++------------
1 file changed, 23 insertions(+), 12 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5a5e5f0..16a0701 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6549,18 +6549,29 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
goto do_fault;
}
- /* The starting level depends on the virtual address size (which can be
- * up to 48 bits) and the translation granule size. It indicates the number
- * of strides (granule_sz bits at a time) needed to consume the bits
- * of the input address. In the pseudocode this is:
- * level = 4 - RoundUp((inputsize - grainsize) / stride)
- * where their 'inputsize' is our 'va_size - tsz', 'grainsize' is
- * our 'granule_sz + 3' and 'stride' is our 'granule_sz'.
- * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
- * = 4 - (va_size - tsz - granule_sz - 3 + granule_sz - 1) / granule_sz
- * = 4 - (va_size - tsz - 4) / granule_sz;
- */
- level = 4 - (va_size - tsz - 4) / granule_sz;
+ if (mmu_idx != ARMMMUIdx_S2NS) {
+ /* The starting level depends on the virtual address size (which can
+ * be up to 48 bits) and the translation granule size. It indicates
+ * the number of strides (granule_sz bits at a time) needed to
+ * consume the bits of the input address. In the pseudocode this is:
+ * level = 4 - RoundUp((inputsize - grainsize) / stride)
+ * where their 'inputsize' is our 'va_size - tsz', 'grainsize' is
+ * our 'granule_sz + 3' and 'stride' is our 'granule_sz'.
+ * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
+ * = 4 - (va_size - tsz - granule_sz - 3 + granule_sz - 1) / granule_sz
+ * = 4 - (va_size - tsz - 4) / granule_sz;
+ */
+ level = 4 - (va_size - tsz - 4) / granule_sz;
+ } else {
+ unsigned int startlevel = extract32(tcr->raw_tcr, 6, 2);
+ if (granule_sz == 9) {
+ /* 4K pages */
+ level = 2 - startlevel;
+ } else {
+ /* 16K or 64K pages */
+ level = 3 - startlevel;
+ }
+ }
/* Clear the vaddr bits which aren't part of the within-region address,
* so that we don't have to special case things when calculating the
--
1.9.1
- [Qemu-devel] [PATCH v2 0/8] arm: Steps towards EL2 support round 5, Edgar E. Iglesias, 2015/10/08
- [Qemu-devel] [PATCH v2 1/8] target-arm: Add HPFAR_EL2, Edgar E. Iglesias, 2015/10/08
- [Qemu-devel] [PATCH v2 7/8] target-arm: Route S2 MMU faults to EL2, Edgar E. Iglesias, 2015/10/08
- Re: [Qemu-devel] [PATCH v2 0/8] arm: Steps towards EL2 support round 5, Edgar E. Iglesias, 2015/10/08
- [Qemu-devel] [PATCH v2 2/8] target-arm: Add computation of starting level for S2 PTW,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v2 3/8] target-arm: Add support for S2 page-table protection bits, Edgar E. Iglesias, 2015/10/08
- [Qemu-devel] [PATCH v2 4/8] target-arm: Avoid inline for get_phys_addr, Edgar E. Iglesias, 2015/10/08
- [Qemu-devel] [PATCH v2 5/8] target-arm: Add ARMMMUFaultInfo, Edgar E. Iglesias, 2015/10/08
- [Qemu-devel] [PATCH v2 6/8] target-arm: Add S2 translation support for S1 PTW, Edgar E. Iglesias, 2015/10/08
- [Qemu-devel] [PATCH v2 8/8] target-arm: Add support for S1 + S2 MMU translations, Edgar E. Iglesias, 2015/10/08