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Re: [Qemu-devel] [Qemu-ppc] [PATCH 13/77] ppc: tlbie, tlbia and tlbisync
From: |
Benjamin Herrenschmidt |
Subject: |
Re: [Qemu-devel] [Qemu-ppc] [PATCH 13/77] ppc: tlbie, tlbia and tlbisync are HV only |
Date: |
Mon, 16 Nov 2015 21:21:36 +1100 |
On Mon, 2015-11-16 at 16:34 +1100, David Gibson wrote:
> On Wed, Nov 11, 2015 at 11:27:26AM +1100, Benjamin Herrenschmidt
> wrote:
> > Not that anything remotely recent supports tlbia but ...
> >
> > Signed-off-by: Benjamin Herrenschmidt <address@hidden>
> > ---
> > target-ppc/translate.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> > index 10eb9e3..014fe5e 100644
> > --- a/target-ppc/translate.c
> > +++ b/target-ppc/translate.c
> > @@ -4836,7 +4836,7 @@ static void gen_tlbia(DisasContext *ctx)
> > #if defined(CONFIG_USER_ONLY)
> > gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> > #else
> > - if (unlikely(ctx->pr)) {
> > + if (unlikely(ctx->pr || !ctx->hv)) {
>
> If I'm reading your previous patch correctly, ctx->hv won't be set
> with in problem state, so I think the ctx->pr check is redundant.
Ah you are right. I do have second thoughts about that previous patch
now that you mention it however. In the real MSR, HV and PR are
independant, I wonder if I'm better off making the check explicit...
The reason I did it this way is that afaik, there is no such thing
as a usermode hypervisor resource in the architecture, so any
hypervisor resource is also a supervisor mode one, but having
ctx->hv be 0 when MSR:HV=1 + MSR:PR=1 might make it easy to write
incorrect code in other places when deciding for example how to direct
interrupts.
I'll need to think a bit more about this one.
> > gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> > return;
> > }
> > @@ -4850,7 +4850,7 @@ static void gen_tlbiel(DisasContext *ctx)
> > #if defined(CONFIG_USER_ONLY)
> > gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> > #else
> > - if (unlikely(ctx->pr)) {
> > + if (unlikely(ctx->pr || !ctx->hv)) {
> > gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> > return;
> > }
> > @@ -4864,7 +4864,7 @@ static void gen_tlbie(DisasContext *ctx)
> > #if defined(CONFIG_USER_ONLY)
> > gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> > #else
> > - if (unlikely(ctx->pr)) {
> > + if (unlikely(ctx->pr || !ctx->hv)) {
> > gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> > return;
> > }
>
- [Qemu-devel] [PATCH 09/77] ppc: Fix do_rfi() for rfi emulation, (continued)
- [Qemu-devel] [PATCH 09/77] ppc: Fix do_rfi() for rfi emulation, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-devel] [PATCH 08/77] ppc: Add number of threads per core to the processor definition, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-devel] [PATCH 06/77] ppc: Add macros to register hypervisor mode SPRs, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-devel] [PATCH 14/77] ppc: Change 'invalid' bit mask of tlbiel and tlbie, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-devel] [PATCH 13/77] ppc: tlbie, tlbia and tlbisync are HV only, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-devel] [PATCH 19/77] ppc: Fix POWER7 and POWER8 exception definitions, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-devel] [PATCH 17/77] ppc: Add PPC_64H instruction flag to POWER7 and POWER8, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-devel] [PATCH 20/77] ppc: Fix generation if ISI/DSI vs. HV mode, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-devel] [PATCH 18/77] ppc: Rework POWER7 & POWER8 exception model, Benjamin Herrenschmidt, 2015/11/10