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[Qemu-devel] [PULL v3 24/55] intel_iommu: add support for split irqchip
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL v3 24/55] intel_iommu: add support for split irqchip |
Date: |
Wed, 20 Jul 2016 20:46:25 +0300 |
From: Peter Xu <address@hidden>
In split irqchip mode, IOAPIC is working in user space, only update
kernel irq routes when entry changed. When IR is enabled, we directly
update the kernel with translated messages. It works just like a kernel
cache for the remapping entries.
Since KVM irqfd is using kernel gsi routes to deliver interrupts, as
long as we can support split irqchip, we will support irqfd as
well. Also, since kernel gsi routes will cache translated interrupts,
irqfd delivery will not suffer from any performance impact due to IR.
And, since we supported irqfd, vhost devices will be able to work
seamlessly with IR now. Logically this should contain both vhost-net and
vhost-user case.
Signed-off-by: Paolo Bonzini <address@hidden>
[move trace-events lines into target-i386/trace-events]
Signed-off-by: Peter Xu <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
Makefile.objs | 1 +
include/hw/i386/intel_iommu.h | 1 +
include/hw/i386/x86-iommu.h | 5 +++++
hw/i386/intel_iommu.c | 7 +++++++
target-i386/kvm.c | 27 +++++++++++++++++++++++++++
target-i386/trace-events | 4 ++++
6 files changed, 45 insertions(+)
create mode 100644 target-i386/trace-events
diff --git a/Makefile.objs b/Makefile.objs
index 7f1f0a3..6d5ddcf 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -153,6 +153,7 @@ trace-events-y += hw/alpha/trace-events
trace-events-y += ui/trace-events
trace-events-y += audio/trace-events
trace-events-y += net/trace-events
+trace-events-y += target-i386/trace-events
trace-events-y += target-sparc/trace-events
trace-events-y += target-s390x/trace-events
trace-events-y += target-ppc/trace-events
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index cdbbddd..e048ced 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -26,6 +26,7 @@
#include "hw/i386/x86-iommu.h"
#include "hw/i386/ioapic.h"
#include "hw/pci/msi.h"
+#include "hw/sysbus.h"
#define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
#define INTEL_IOMMU_DEVICE(obj) \
diff --git a/include/hw/i386/x86-iommu.h b/include/hw/i386/x86-iommu.h
index 699dd06..fa6ce31 100644
--- a/include/hw/i386/x86-iommu.h
+++ b/include/hw/i386/x86-iommu.h
@@ -21,6 +21,7 @@
#define IOMMU_COMMON_H
#include "hw/sysbus.h"
+#include "hw/pci/pci.h"
#define TYPE_X86_IOMMU_DEVICE ("x86-iommu")
#define X86_IOMMU_DEVICE(obj) \
@@ -31,6 +32,7 @@
OBJECT_GET_CLASS(X86IOMMUClass, obj, TYPE_X86_IOMMU_DEVICE)
#define X86_IOMMU_PCI_DEVFN_MAX 256
+#define X86_IOMMU_SID_INVALID (0xffff)
typedef struct X86IOMMUState X86IOMMUState;
typedef struct X86IOMMUClass X86IOMMUClass;
@@ -39,6 +41,9 @@ struct X86IOMMUClass {
SysBusDeviceClass parent;
/* Intel/AMD specific realize() hook */
DeviceRealize realize;
+ /* MSI-based interrupt remapping */
+ int (*int_remap)(X86IOMMUState *iommu, MSIMessage *src,
+ MSIMessage *dst, uint16_t sid);
};
struct X86IOMMUState {
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 9066cda..ebc7531 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2165,6 +2165,12 @@ do_not_translate:
return 0;
}
+static int vtd_int_remap(X86IOMMUState *iommu, MSIMessage *src,
+ MSIMessage *dst, uint16_t sid)
+{
+ return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu), src, dst);
+}
+
static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr,
uint64_t *data, unsigned size,
MemTxAttrs attrs)
@@ -2399,6 +2405,7 @@ static void vtd_class_init(ObjectClass *klass, void *data)
dc->props = vtd_properties;
dc->hotpluggable = false;
x86_class->realize = vtd_realize;
+ x86_class->int_remap = vtd_int_remap;
}
static const TypeInfo vtd_info = {
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 9327523..9c00e48 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -35,6 +35,7 @@
#include "hw/i386/apic.h"
#include "hw/i386/apic_internal.h"
#include "hw/i386/apic-msidef.h"
+#include "hw/i386/intel_iommu.h"
#include "exec/ioport.h"
#include "standard-headers/asm-x86/hyperv.h"
@@ -42,6 +43,7 @@
#include "hw/pci/msi.h"
#include "migration/migration.h"
#include "exec/memattrs.h"
+#include "trace.h"
//#define DEBUG_KVM
@@ -3371,6 +3373,31 @@ int kvm_device_msix_deassign(KVMState *s, uint32_t
dev_id)
int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
uint64_t address, uint32_t data, PCIDevice *dev)
{
+ X86IOMMUState *iommu = x86_iommu_get_default();
+
+ if (iommu) {
+ int ret;
+ MSIMessage src, dst;
+ X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
+
+ src.address = route->u.msi.address_hi;
+ src.address <<= VTD_MSI_ADDR_HI_SHIFT;
+ src.address |= route->u.msi.address_lo;
+ src.data = route->u.msi.data;
+
+ ret = class->int_remap(iommu, &src, &dst, dev ? \
+ pci_requester_id(dev) : \
+ X86_IOMMU_SID_INVALID);
+ if (ret) {
+ trace_kvm_x86_fixup_msi_error(route->gsi);
+ return 1;
+ }
+
+ route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
+ route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
+ route->u.msi.data = dst.data;
+ }
+
return 0;
}
diff --git a/target-i386/trace-events b/target-i386/trace-events
new file mode 100644
index 0000000..2113075
--- /dev/null
+++ b/target-i386/trace-events
@@ -0,0 +1,4 @@
+# See docs/trace-events.txt for syntax documentation.
+
+# target-i386/kvm.c
+kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for GSI
%" PRIu32
--
MST
- [Qemu-devel] [PULL v3 14/55] intel_iommu: allow queued invalidation for IR, (continued)
- [Qemu-devel] [PULL v3 14/55] intel_iommu: allow queued invalidation for IR, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 15/55] intel_iommu: set IR bit for ECAP register, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 16/55] acpi: add DMAR scope definition for root IOAPIC, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 17/55] intel_iommu: define interrupt remap table addr register, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 18/55] intel_iommu: handle interrupt remap enable, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 19/55] intel_iommu: define several structs for IOMMU IR, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 20/55] intel_iommu: add IR translation faults defines, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 21/55] intel_iommu: Add support for PCI MSI remap, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 22/55] q35: ioapic: add support for emulated IOAPIC IR, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 23/55] ioapic: introduce ioapic_entry_parse() helper, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 24/55] intel_iommu: add support for split irqchip,
Michael S. Tsirkin <=
- [Qemu-devel] [PULL v3 25/55] x86-iommu: introduce IEC notifiers, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 26/55] ioapic: register IOMMU IEC notifier for ioapic, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 27/55] intel_iommu: Add support for Extended Interrupt Mode, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 28/55] intel_iommu: add SID validation for IR, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 29/55] kvm-irqchip: simplify kvm_irqchip_add_msi_route, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 30/55] kvm-irqchip: i386: add hook for add/remove virq, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 31/55] kvm-irqchip: x86: add msi route notify fn, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 32/55] kvm-irqchip: do explicit commit when update irq, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 33/55] intel_iommu: support all masks in interrupt entry cache invalidation, Michael S. Tsirkin, 2016/07/20
- [Qemu-devel] [PULL v3 34/55] kvm-all: add trace events for kvm irqchip ops, Michael S. Tsirkin, 2016/07/20