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[Qemu-devel] [PATCH RFC v1 18/29] target-arc: J, JL
From: |
Michael Rolnik |
Subject: |
[Qemu-devel] [PATCH RFC v1 18/29] target-arc: J, JL |
Date: |
Fri, 9 Sep 2016 01:31:59 +0300 |
Signed-off-by: Michael Rolnik <address@hidden>
---
target-arc/translate-inst.c | 93 +++++++++++++++++++++++++++++++++++++++++++++
target-arc/translate-inst.h | 3 ++
2 files changed, 96 insertions(+)
diff --git a/target-arc/translate-inst.c b/target-arc/translate-inst.c
index ed2ced0..fd49a16 100644
--- a/target-arc/translate-inst.c
+++ b/target-arc/translate-inst.c
@@ -1976,3 +1976,96 @@ gen_set_label(label_done);
return BS_BRANCH_DS;
}
+/*
+ J
+*/
+int arc_gen_J(DisasCtxt *ctx, TCGv src1, ARC_COND cond)
+{
+ TCGLabel *label_done = gen_new_label();
+ TCGLabel *label_fall = gen_new_label();
+
+ arc_gen_jump_ifnot(ctx, cond, label_fall);
+
+ if (ctx->opt.f) {
+ if (TCGV_EQUAL(src1, cpu_ilink1)) {
+ tcg_gen_mov_tl(cpu_Lf, cpu_l1_Lf);
+ tcg_gen_mov_tl(cpu_Zf, cpu_l1_Zf);
+ tcg_gen_mov_tl(cpu_Nf, cpu_l1_Nf);
+ tcg_gen_mov_tl(cpu_Cf, cpu_l1_Cf);
+ tcg_gen_mov_tl(cpu_Vf, cpu_l1_Vf);
+ tcg_gen_mov_tl(cpu_Uf, cpu_l1_Uf);
+
+ tcg_gen_mov_tl(cpu_DEf, cpu_l1_DEf);
+ tcg_gen_mov_tl(cpu_AEf, cpu_l1_AEf);
+ tcg_gen_mov_tl(cpu_A2f, cpu_l1_A2f);
+ tcg_gen_mov_tl(cpu_A1f, cpu_l1_A1f);
+ tcg_gen_mov_tl(cpu_E2f, cpu_l1_E2f);
+ tcg_gen_mov_tl(cpu_E1f, cpu_l1_E1f);
+
+ tcg_gen_mov_tl(cpu_bta, cpu_bta_l1);
+ }
+ if (TCGV_EQUAL(src1, cpu_ilink2)) {
+ tcg_gen_mov_tl(cpu_Lf, cpu_l2_Lf);
+ tcg_gen_mov_tl(cpu_Zf, cpu_l2_Zf);
+ tcg_gen_mov_tl(cpu_Nf, cpu_l2_Nf);
+ tcg_gen_mov_tl(cpu_Cf, cpu_l2_Cf);
+ tcg_gen_mov_tl(cpu_Vf, cpu_l2_Vf);
+ tcg_gen_mov_tl(cpu_Uf, cpu_l2_Uf);
+
+ tcg_gen_mov_tl(cpu_DEf, cpu_l2_DEf);
+ tcg_gen_mov_tl(cpu_AEf, cpu_l2_AEf);
+ tcg_gen_mov_tl(cpu_A2f, cpu_l2_A2f);
+ tcg_gen_mov_tl(cpu_A1f, cpu_l2_A1f);
+ tcg_gen_mov_tl(cpu_E2f, cpu_l2_E2f);
+ tcg_gen_mov_tl(cpu_E1f, cpu_l2_E1f);
+
+ tcg_gen_mov_tl(cpu_bta, cpu_bta_l2);
+ }
+ }
+
+ tcg_gen_mov_tl(cpu_pc, src1);
+ if (ctx->opt.d == 0) {
+ arc_gen_kill_delayslot(ctx);
+ } else {
+ arc_gen_exec_delayslot(ctx);
+ }
+ tcg_gen_br(label_done);
+
+gen_set_label(label_fall);
+ tcg_gen_movi_tl(cpu_pc, ctx->dpc);
+ arc_gen_exec_delayslot(ctx);
+
+gen_set_label(label_done);
+
+ return BS_BRANCH_DS;
+}
+
+/*
+ JL
+*/
+int arc_gen_JL(DisasCtxt *ctx, TCGv src1, ARC_COND cond)
+{
+ TCGLabel *label_done = gen_new_label();
+ TCGLabel *label_fall = gen_new_label();
+
+ arc_gen_jump_ifnot(ctx, cond, label_fall);
+
+ tcg_gen_mov_tl(cpu_pc, src1);
+ if (ctx->opt.d == 0) {
+ tcg_gen_movi_tl(cpu_blink, ctx->npc);
+ arc_gen_kill_delayslot(ctx);
+ } else {
+ tcg_gen_movi_tl(cpu_blink, ctx->dpc);
+ arc_gen_exec_delayslot(ctx);
+ }
+ tcg_gen_br(label_done);
+
+gen_set_label(label_fall);
+ tcg_gen_movi_tl(cpu_pc, ctx->dpc);
+ arc_gen_exec_delayslot(ctx);
+
+gen_set_label(label_done);
+
+ return BS_BRANCH_DS;
+}
+
diff --git a/target-arc/translate-inst.h b/target-arc/translate-inst.h
index 065570e..7d76707 100644
--- a/target-arc/translate-inst.h
+++ b/target-arc/translate-inst.h
@@ -138,3 +138,6 @@ void arc_gen_jump_ifnot(DisasCtxt *ctx, ARC_COND cond,
TCGLabel *label_skip);
int arc_gen_B(DisasCtxt *c, TCGv rd, ARC_COND cond);
int arc_gen_BL(DisasCtxt *c, TCGv Rd, ARC_COND cond);
+int arc_gen_J(DisasCtxt *c, TCGv src1, ARC_COND cond);
+int arc_gen_JL(DisasCtxt *c, TCGv src1, ARC_COND cond);
+
--
2.4.9 (Apple Git-60)
- Re: [Qemu-devel] [PATCH RFC v1 11/29] target-arc: BCLR, BMSK, BSET, BTST, BXOR, (continued)
- [Qemu-devel] [PATCH RFC v1 13/29] target-arc: NORM, NORMW, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 15/29] target-arc: MUL64, MULU64, DIVAW, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 12/29] target-arc: RLC, RRC, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 14/29] target-arc: MPY, MPYH, MPYHU, MPYU, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 16/29] target-arc: BBIT0, BBIT1, BR, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 18/29] target-arc: J, JL,
Michael Rolnik <=
- [Qemu-devel] [PATCH RFC v1 17/29] target-arc: B, BL, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 19/29] target-arc: LR, SR, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 22/29] target-arc: ASLS, ASRS, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 20/29] target-arc: ADDS, ADDSDW, SUBS, SUBSDW, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 21/29] target-arc: ABSS, ABSSW, NEGS, NEGSW, RND16, SAT16, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 23/29] target-arc: FLAG, BRK, SLEEP, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 25/29] target-arc: TRAP, SWI, Michael Rolnik, 2016/09/08