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[Qemu-devel] [PATCH 04/29] target-sparc: add UltraSPARC T1 TLB #defines
From: |
Artyom Tarasenko |
Subject: |
[Qemu-devel] [PATCH 04/29] target-sparc: add UltraSPARC T1 TLB #defines |
Date: |
Sat, 1 Oct 2016 12:05:08 +0200 |
Signed-off-by: Artyom Tarasenko <address@hidden>
---
target-sparc/cpu.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 2c169e1..bafa8d9 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -328,6 +328,10 @@ enum {
#define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL)
#define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL)
+/* UltraSPARC T1 specific */
+#define TLB_UST1_IS_REAL_BIT (1ULL << 9) /* Real translation entry */
+#define TLB_UST1_IS_SUN4V_BIT (1ULL << 10) /* sun4u/sun4v TTE format switch */
+
#define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */
#define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */
#define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */
--
2.7.2
- [Qemu-devel] [PATCH 02/29] target-sparc: use explicit mmu register pointers, (continued)
- [Qemu-devel] [PATCH 02/29] target-sparc: use explicit mmu register pointers, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 03/29] target-sparc: add UA2005 TTE bit #defines, Artyom Tarasenko, 2016/10/01
- Re: [Qemu-devel] [PATCH 03/29] target-sparc: add UA2005 TTE bit #defines, Richard Henderson, 2016/10/10
- Re: [Qemu-devel] [PATCH 03/29] target-sparc: add UA2005 TTE bit #defines, Artyom Tarasenko, 2016/10/10
- Re: [Qemu-devel] [PATCH 03/29] target-sparc: add UA2005 TTE bit #defines, Richard Henderson, 2016/10/11
- Re: [Qemu-devel] [PATCH 03/29] target-sparc: add UA2005 TTE bit #defines, Artyom Tarasenko, 2016/10/11
- Re: [Qemu-devel] [PATCH 03/29] target-sparc: add UA2005 TTE bit #defines, Richard Henderson, 2016/10/11
- Re: [Qemu-devel] [PATCH 03/29] target-sparc: add UA2005 TTE bit #defines, Artyom Tarasenko, 2016/10/12
- Re: [Qemu-devel] [PATCH 03/29] target-sparc: add UA2005 TTE bit #defines, Richard Henderson, 2016/10/12
[Qemu-devel] [PATCH 04/29] target-sparc: add UltraSPARC T1 TLB #defines,
Artyom Tarasenko <=
[Qemu-devel] [PATCH 06/29] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE, Artyom Tarasenko, 2016/10/01
[Qemu-devel] [PATCH 05/29] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode, Artyom Tarasenko, 2016/10/01
[Qemu-devel] [PATCH 08/29] target-sparc: implement UltraSPARC-T1 Strand status ASR, Artyom Tarasenko, 2016/10/01
[Qemu-devel] [PATCH 07/29] target-sparc: implement UA2005 scratchpad registers, Artyom Tarasenko, 2016/10/01
[Qemu-devel] [PATCH 09/29] target-sparc: hypervisor mode takes over nucleus mode, Artyom Tarasenko, 2016/10/01