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[Qemu-devel] [PATCH v3 05/11] tcg-mips: Adjust move functions for mips64
From: |
Jin Guojie |
Subject: |
[Qemu-devel] [PATCH v3 05/11] tcg-mips: Adjust move functions for mips64 |
Date: |
Fri, 25 Nov 2016 11:31:38 +0800 |
tcg_out_mov: using OPC_OR as most mips assemblers do;
tcg_out_movi: extended to 64-bit immediate.
Cc: Aurelien Jarno <address@hidden>
Cc: James Hogan <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Jin Guojie <address@hidden>
---
tcg/mips/tcg-target.inc.c | 34 +++++++++++++++++++++++++---------
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 88dd344..f0bf77d 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -544,23 +544,39 @@ static inline void tcg_out_mov(TCGContext *s, TCGType
type,
{
/* Simple reg-reg move, optimising out the 'do nothing' case */
if (ret != arg) {
- tcg_out_opc_reg(s, OPC_ADDU, ret, arg, TCG_REG_ZERO);
+ tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
}
}
-static inline void tcg_out_movi(TCGContext *s, TCGType type,
- TCGReg reg, tcg_target_long arg)
+static void tcg_out_movi(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long arg)
{
+ if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
+ arg = (int32_t)arg;
+ }
if (arg == (int16_t)arg) {
- tcg_out_opc_imm(s, OPC_ADDIU, reg, TCG_REG_ZERO, arg);
- } else if (arg == (uint16_t)arg) {
- tcg_out_opc_imm(s, OPC_ORI, reg, TCG_REG_ZERO, arg);
+ tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
+ return;
+ }
+ if (arg == (uint16_t)arg) {
+ tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
+ return;
+ }
+ if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
+ tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
} else {
- tcg_out_opc_imm(s, OPC_LUI, reg, TCG_REG_ZERO, arg >> 16);
- if (arg & 0xffff) {
- tcg_out_opc_imm(s, OPC_ORI, reg, reg, arg & 0xffff);
+ tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
+ if (arg & 0xffff0000ull) {
+ tcg_out_dsll(s, ret, ret, 16);
+ tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
+ tcg_out_dsll(s, ret, ret, 16);
+ } else {
+ tcg_out_dsll(s, ret, ret, 32);
}
}
+ if (arg & 0xffff) {
+ tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
+ }
}
static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
--
2.1.0
- [Qemu-devel] [PATCH v3 00/11] tcg mips64 and mips r6 improvements, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 01/11] tcg-mips: Move bswap code to a subroutine, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 02/11] tcg-mips: Add mips64 opcodes, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 03/11] tcg-mips: Support 64-bit opcodes, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 04/11] tcg-mips: Add bswap32u and bswap64, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 05/11] tcg-mips: Adjust move functions for mips64,
Jin Guojie <=
- [Qemu-devel] [PATCH v3 06/11] tcg-mips: Adjust load/store functions for mips64, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 08/11] tcg-mips: Add tcg unwind info, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 09/11] tcg-mips: Adjust calling conventions for mips64, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 07/11] tcg-mips: Adjust prologue for mips64, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 11/11] tcg-mips: Adjust condition functions for mips64, Jin Guojie, 2016/11/24
- [Qemu-devel] [PATCH v3 10/11] tcg-mips: Adjust qemu_ld/st for mips64, Jin Guojie, 2016/11/24
- Re: [Qemu-devel] [PATCH v3 00/11] tcg mips64 and mips r6 improvements, Aurelien Jarno, 2016/11/25