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[Qemu-devel] [PULL 02/25] cadence_uart: Check if receiver timeout counte
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 02/25] cadence_uart: Check if receiver timeout counter is disabled |
Date: |
Tue, 27 Dec 2016 15:20:54 +0000 |
From: Andrew Gacek <address@hidden>
When register Rcvr_timeout_reg0 (R_RTOR in cadence_uart.c) is set to
0, the receiver timeout counter should be disabled. See page 1801 of
"Zynq-7000 AP SoC Technical Reference Manual". This commit adds a
such a check before setting the receive timeout interrupt.
Signed-off-by: Andrew Gacek <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/char/cadence_uart.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index dba1c53..4dcee57 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -138,9 +138,10 @@ static void fifo_trigger_update(void *opaque)
{
CadenceUARTState *s = opaque;
- s->r[R_CISR] |= UART_INTR_TIMEOUT;
-
- uart_update_status(s);
+ if (s->r[R_RTOR]) {
+ s->r[R_CISR] |= UART_INTR_TIMEOUT;
+ uart_update_status(s);
+ }
}
static void uart_rx_reset(CadenceUARTState *s)
--
2.7.4
- [Qemu-devel] [PULL 00/25] target-arm queue, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 01/25] cadence_uart: Check baud rate generator and divider values on migration, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 02/25] cadence_uart: Check if receiver timeout counter is disabled,
Peter Maydell <=
- [Qemu-devel] [PULL 03/25] Correct value of ARM Cortex-A8 MVFR1 register., Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 04/25] target-arm: Fix aarch64 vec_reg_offset, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 05/25] target-arm: Fix aarch64 disas_ldst_single_struct, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 06/25] hw/intc/arm_gicv3_common: fix aff3 in typer, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 07/25] target-arm: Log AArch64 exception returns, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 08/25] hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 09/25] hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 10/25] hw/arm/virt: add 2.9 machine type, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 11/25] m25p80: add support for the mx66l1g45g, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 12/25] aspeed: QOMify the CPU object and attach it to the SoC, Peter Maydell, 2016/12/27