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[Qemu-devel] [PULL 16/24] target/openrisc: Enable trap, csync, msync, ps
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 16/24] target/openrisc: Enable trap, csync, msync, psync for user mode |
Date: |
Tue, 14 Feb 2017 08:25:28 +1100 |
Not documented as disabled for user mode.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/openrisc/translate.c | 32 --------------------------------
1 file changed, 32 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index f91ab6a..6c8f05c 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1134,52 +1134,20 @@ static void dec_sys(DisasContext *dc, uint32_t insn)
case 0x100: /* l.trap */
LOG_DIS("l.trap %d\n", K16);
-#if defined(CONFIG_USER_ONLY)
- return;
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
- gen_illegal_exception(dc);
- return;
- }
tcg_gen_movi_tl(cpu_pc, dc->pc);
gen_exception(dc, EXCP_TRAP);
-#endif
break;
case 0x300: /* l.csync */
LOG_DIS("l.csync\n");
-#if defined(CONFIG_USER_ONLY)
- return;
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
- gen_illegal_exception(dc);
- return;
- }
-#endif
break;
case 0x200: /* l.msync */
LOG_DIS("l.msync\n");
-#if defined(CONFIG_USER_ONLY)
- return;
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
- gen_illegal_exception(dc);
- return;
- }
-#endif
break;
case 0x270: /* l.psync */
LOG_DIS("l.psync\n");
-#if defined(CONFIG_USER_ONLY)
- return;
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
- gen_illegal_exception(dc);
- return;
- }
-#endif
break;
default:
--
2.9.3
- [Qemu-devel] [PULL 05/24] target/openrisc: Fix exception handling status registers, (continued)
- [Qemu-devel] [PULL 05/24] target/openrisc: Fix exception handling status registers, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 07/24] target/openrisc: Tidy insn dumping, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 06/24] target/openrisc: Implement lwa, swa, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 08/24] target/openrisc: Rationalize immediate extraction, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 10/24] target/openrisc: Put SR[OVE] in TB flags, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 11/24] target/openrisc: Invert the decoding in dec_calc, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 09/24] target/openrisc: Streamline arithmetic and OVE, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 12/24] target/openrisc: Keep SR_F in a separate variable, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 14/24] target/openrisc: Use movcond where appropriate, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 13/24] target/openrisc: Keep SR_CY and SR_OV in a separate variables, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 16/24] target/openrisc: Enable trap, csync, msync, psync for user mode,
Richard Henderson <=
- [Qemu-devel] [PULL 15/24] target/openrisc: Set flags on helpers, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 17/24] target/openrisc: Implement msync, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 18/24] target/openrisc: Represent MACHI:MACLO as a single unit, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 20/24] target/openrisc: Fix madd, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 19/24] target/openrisc: Implement muld, muldu, macu, msbu, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 21/24] target/openrisc: Optimize l.jal to next, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 22/24] target/openrisc: Tidy ppc/npc implementation, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 23/24] target/openrisc: Tidy handling of delayed branches, Richard Henderson, 2017/02/13
- [Qemu-devel] [PULL 24/24] target/openrisc: Optimize for r0 being zero, Richard Henderson, 2017/02/13
- Re: [Qemu-devel] [PULL 00/24] target/openrisc patches, Peter Maydell, 2017/02/14