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[Qemu-devel] [PULL 13/15] target/sh4: movua.l is an SH4-A only instructi
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PULL 13/15] target/sh4: movua.l is an SH4-A only instruction |
Date: |
Sat, 13 May 2017 11:32:46 +0200 |
At the same time change the comment describing the instruction the same
way than other instruction, so that the code is easier to read and search.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
---
target/sh4/translate.c | 26 +++++++++++++++-----------
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index baed19bdac..4bb9105865 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1501,17 +1501,21 @@ static void _decode_opc(DisasContext * ctx)
}
ctx->has_movcal = 1;
return;
- case 0x40a9:
- /* MOVUA.L @Rm,R0 (Rm) -> R0
- Load non-boundary-aligned data */
- tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
- return;
- case 0x40e9:
- /* MOVUA.L @Rm+,R0 (Rm) -> R0, Rm + 4 -> Rm
- Load non-boundary-aligned data */
- tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
- tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
- return;
+ case 0x40a9: /* movua.l @Rm,R0 */
+ /* Load non-boundary-aligned data */
+ if (ctx->features & SH_FEATURE_SH4A) {
+ tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
+ return;
+ }
+ break;
+ case 0x40e9: /* movua.l @Rm+,R0 */
+ /* Load non-boundary-aligned data */
+ if (ctx->features & SH_FEATURE_SH4A) {
+ tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
+ tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
+ return;
+ }
+ break;
case 0x0029: /* movt Rn */
tcg_gen_mov_i32(REG(B11_8), cpu_sr_t);
return;
--
2.11.0
- [Qemu-devel] [PULL 00/15] Queued target/sh4 patches, Aurelien Jarno, 2017/05/13
- [Qemu-devel] [PULL 13/15] target/sh4: movua.l is an SH4-A only instruction,
Aurelien Jarno <=
- [Qemu-devel] [PULL 12/15] target/sh4: implement tas.b using atomic helper, Aurelien Jarno, 2017/05/13
- [Qemu-devel] [PULL 05/15] target/sh4: fix BS_STOP exit, Aurelien Jarno, 2017/05/13
- [Qemu-devel] [PULL 03/15] target/sh4: do not include DELAY_SLOT_TRUE in the TB state, Aurelien Jarno, 2017/05/13
- [Qemu-devel] [PULL 15/15] target/sh4: use cpu_loop_exit_restore, Aurelien Jarno, 2017/05/13
- [Qemu-devel] [PULL 08/15] target/sh4: fold ctx->bstate = BS_BRANCH into gen_conditional_jump, Aurelien Jarno, 2017/05/13
- [Qemu-devel] [PULL 01/15] target/sh4: split ctx->flags into ctx->tbflags and ctx->envflags, Aurelien Jarno, 2017/05/13
- [Qemu-devel] [PULL 11/15] target/sh4: generate fences for SH4, Aurelien Jarno, 2017/05/13
- [Qemu-devel] [PULL 09/15] target/sh4: optimize gen_store_fpr64, Aurelien Jarno, 2017/05/13
- [Qemu-devel] [PULL 10/15] target/sh4: optimize gen_write_sr using extract op, Aurelien Jarno, 2017/05/13
- [Qemu-devel] [PULL 06/15] target/sh4: fix BS_EXCP exit, Aurelien Jarno, 2017/05/13