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[Qemu-devel] [PATCH 14/19] nvic: Disable the non-secure HardFault if AIR
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 14/19] nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear |
Date: |
Tue, 12 Sep 2017 19:14:01 +0100 |
If AIRCR.BFHFNMINS is clear, then although NonSecure HardFault
can still be pended via SHCSR.HARDFAULTPENDED it mustn't actually
preempt execution. The simple way to achieve this is to clear the
enable bit for it, since the enable bit isn't guest visible.
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/armv7m_nvic.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index db2f170..91d2f33 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -937,11 +937,16 @@ static void nvic_writel(NVICState *s, uint32_t offset,
uint32_t value,
(R_V7M_AIRCR_SYSRESETREQS_MASK |
R_V7M_AIRCR_BFHFNMINS_MASK |
R_V7M_AIRCR_PRIS_MASK);
- /* BFHFNMINS changes the priority of Secure HardFault */
+ /* BFHFNMINS changes the priority of Secure HardFault, and
+ * allows a pending Non-secure HardFault to preempt (which
+ * we implement by marking it enabled).
+ */
if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
} else {
s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
}
}
nvic_irq_update(s);
@@ -1562,7 +1567,6 @@ static void armv7m_nvic_reset(DeviceState *dev)
NVICState *s = NVIC(dev);
s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
- s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
/* MEM, BUS, and USAGE are enabled through
* the System Handler Control register
*/
@@ -1584,6 +1588,10 @@ static void armv7m_nvic_reset(DeviceState *dev)
/* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
+ /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
+ } else {
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
}
/* Strictly speaking the reset handler should be enabled.
--
2.7.4
- [Qemu-devel] [PATCH 17/19] nvic: Make ICSR banked for v8M, (continued)
- [Qemu-devel] [PATCH 17/19] nvic: Make ICSR banked for v8M, Peter Maydell, 2017/09/12
- [Qemu-devel] [PATCH 09/19] nvic: Make set_pending and clear_pending take a secure parameter, Peter Maydell, 2017/09/12
- [Qemu-devel] [PATCH 01/19] target/arm: Implement MSR/MRS access to NS banked registers, Peter Maydell, 2017/09/12
- [Qemu-devel] [PATCH 07/19] nvic: Implement NVIC_ITNS<n> registers, Peter Maydell, 2017/09/12
- [Qemu-devel] [PATCH 12/19] nvic: In escalation to HardFault, support HF not being priority -1, Peter Maydell, 2017/09/12
- [Qemu-devel] [PATCH 14/19] nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear,
Peter Maydell <=
- [Qemu-devel] [PATCH 10/19] nvic: Make SHPR registers banked, Peter Maydell, 2017/09/12
- [Qemu-devel] [PATCH 13/19] nvic: Implement v8M changes to fixed priority exceptions, Peter Maydell, 2017/09/12
- [Qemu-devel] [PATCH 19/19] nvic: Support banked exceptions in acknowledge and complete, Peter Maydell, 2017/09/12
- [Qemu-devel] [PATCH 18/19] nvic: Make SHCSR banked for v8M, Peter Maydell, 2017/09/12
- Re: [Qemu-devel] [PATCH 00/19] ARMv8M: support security extn in the NVIC, no-reply, 2017/09/19