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[Qemu-devel] [PATCH 26/38] target/hppa: Implement LCI
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 26/38] target/hppa: Implement LCI |
Date: |
Thu, 28 Dec 2017 22:31:33 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/hppa/translate.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index ec61c57e55..2e3edf8957 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2453,6 +2453,25 @@ static DisasJumpType trans_lpa(DisasContext *ctx,
uint32_t insn,
return nullify_end(ctx, DISAS_NEXT);
}
+
+static DisasJumpType trans_lci(DisasContext *ctx, uint32_t insn,
+ const DisasInsn *di)
+{
+ unsigned rt = extract32(insn, 0, 5);
+ TCGv_reg ci;
+
+ CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
+
+ /* The Coherence Index is an implementation-defined function of the
+ physical address. Two addresses with the same CI have a coherent
+ view of the cache. Our implementation is to return 0 for all,
+ since the entire address space is coherent. */
+ ci = tcg_const_reg(0);
+ save_gpr(ctx, rt, ci);
+ tcg_temp_free(ci);
+
+ return DISAS_NEXT;
+}
#endif /* !CONFIG_USER_ONLY */
static const DisasInsn table_mem_mgmt[] = {
@@ -2481,6 +2500,7 @@ static const DisasInsn table_mem_mgmt[] = {
{ 0x04001200u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlb */
{ 0x04001240u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlbe */
{ 0x04001340u, 0xfc003fc0u, trans_lpa },
+ { 0x04001300u, 0xfc003fe0u, trans_lci },
#endif
};
--
2.14.3
- [Qemu-devel] [PATCH 23/38] target/hppa: Implement P*TLB and P*TLBE insns, (continued)
- [Qemu-devel] [PATCH 23/38] target/hppa: Implement P*TLB and P*TLBE insns, Richard Henderson, 2017/12/29
- [Qemu-devel] [PATCH 24/38] target/hppa: Implement LDWA, Richard Henderson, 2017/12/29
- [Qemu-devel] [PATCH 17/38] target/hppa: Implement IASQ, Richard Henderson, 2017/12/29
- [Qemu-devel] [PATCH 19/38] target/hppa: Implement external interrupts, Richard Henderson, 2017/12/29
- [Qemu-devel] [PATCH 22/38] target/hppa: Implement I*TLBA and I*TLBP insns, Richard Henderson, 2017/12/29
- [Qemu-devel] [PATCH 20/38] target/hppa: Implement the interval timer, Richard Henderson, 2017/12/29
- [Qemu-devel] [PATCH 21/38] target/hppa: Log unimplemented instructions, Richard Henderson, 2017/12/29
- [Qemu-devel] [PATCH 25/38] target/hppa: Implement LPA, Richard Henderson, 2017/12/29
- [Qemu-devel] [PATCH 28/38] target/hppa: Implement a halt instruction, Richard Henderson, 2017/12/29
- [Qemu-devel] [PATCH 27/38] target/hppa: Implement SYNCDMA insn, Richard Henderson, 2017/12/29
- [Qemu-devel] [PATCH 26/38] target/hppa: Implement LCI,
Richard Henderson <=
- [Qemu-devel] [PATCH 31/38] target/hppa: Add system registers to gdbstub, Richard Henderson, 2017/12/29
- [Qemu-devel] [PATCH 32/38] target/hppa: Add migration for the cpu, Richard Henderson, 2017/12/29
- [Qemu-devel] [PATCH 29/38] hw/hppa: Implement DINO system board, Richard Henderson, 2017/12/29
- [Qemu-devel] [PATCH 30/38] target/hppa: Optimize for flat addressing space, Richard Henderson, 2017/12/29
- [Qemu-devel] [PATCH 33/38] target/hppa: Implement B,GATE insn, Richard Henderson, 2017/12/29
- [Qemu-devel] [PATCH 35/38] qom: Add MMU_DEBUG_LOAD, Richard Henderson, 2017/12/29
- [Qemu-devel] [PATCH 34/38] target/hppa: Only use EXCP_DTLB_MISS, Richard Henderson, 2017/12/29
- [Qemu-devel] [PATCH 36/38] target/hppa: Use MMU_DEBUG_LOAD when reloading for CR[IIR], Richard Henderson, 2017/12/29