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[Qemu-devel] [PULL 16/24] RISC-V: Hardwire satp to 0 for no-mmu case
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PULL 16/24] RISC-V: Hardwire satp to 0 for no-mmu case |
Date: |
Wed, 21 Mar 2018 13:46:52 -0700 |
satp is WARL so it should not trap on illegal writes, rather
it can be hardwired to zero and silently ignore illegal writes.
It seems the RISC-V WARL behaviour is preferred to having to
trap overhead versus simply reading back the value and checking
if the write took (saves hundreds of cycles and more complex
trap handling code).
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/op_helper.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index e34715d..dd3e417 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -242,7 +242,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
}
case CSR_SATP: /* CSR_SPTBR */ {
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
- goto do_illegal;
+ break;
}
if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val_to_write ^
env->sptbr))
{
@@ -452,7 +452,10 @@ target_ulong csr_read_helper(CPURISCVState *env,
target_ulong csrno)
return env->scounteren;
case CSR_SCAUSE:
return env->scause;
- case CSR_SPTBR:
+ case CSR_SATP: /* CSR_SPTBR */
+ if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+ return 0;
+ }
if (env->priv_ver >= PRIV_VERSION_1_10_0) {
return env->satp;
} else {
--
2.7.0
- [Qemu-devel] [PULL 18/24] RISC-V: riscv-qemu port supports sv39 and sv48, (continued)
- [Qemu-devel] [PULL 18/24] RISC-V: riscv-qemu port supports sv39 and sv48, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 20/24] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 19/24] RISC-V: vectored traps are optional, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 09/24] RISC-V: Include intruction hex in disassembly, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 08/24] RISC-V: Make sure rom has space for fdt, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 10/24] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 13/24] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 12/24] RISC-V: Make some header guards more specific, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 15/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 23/24] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 16/24] RISC-V: Hardwire satp to 0 for no-mmu case,
Michael Clark <=
- [Qemu-devel] [PULL 21/24] RISC-V: Remove support for adhoc X_COP interrupt, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 22/24] RISC-V: Convert cpu definition towards future model, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 24/24] RISC-V: Remove erroneous comment from translate.c, Michael Clark, 2018/03/21
- Re: [Qemu-devel] [PULL 00/24] RISC-V: Post-merge spec conformance and cleanup v5, Michael Clark, 2018/03/24