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[Qemu-devel] [PULL 21/24] RISC-V: Remove support for adhoc X_COP interru
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PULL 21/24] RISC-V: Remove support for adhoc X_COP interrupt |
Date: |
Wed, 21 Mar 2018 13:46:57 -0700 |
This is essentially dead-code elimination. Support for more
local interrupts will be added in a future revision, as they
will be defined in a future version of the Privileged ISA
specification.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu_bits.h | 1 -
target/riscv/op_helper.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 12b4757..133e070 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -346,7 +346,6 @@
#define IRQ_S_EXT 9
#define IRQ_H_EXT 10 /* until: priv-1.9.1 */
#define IRQ_M_EXT 11 /* until: priv-1.9.1 */
-#define IRQ_X_COP 12 /* non-standard */
/* Default addresses */
#define DEFAULT_RSTVEC 0x00001000
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index ba3639d..1fdde90 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -90,7 +90,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
target_ulong csrno)
{
#ifndef CONFIG_USER_ONLY
- uint64_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 <<
IRQ_X_COP);
+ uint64_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP;
uint64_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
#endif
--
2.7.0
- [Qemu-devel] [PULL 20/24] RISC-V: No traps on writes to misa, minstret, mcycle, (continued)
- [Qemu-devel] [PULL 20/24] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 19/24] RISC-V: vectored traps are optional, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 09/24] RISC-V: Include intruction hex in disassembly, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 08/24] RISC-V: Make sure rom has space for fdt, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 10/24] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 13/24] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 12/24] RISC-V: Make some header guards more specific, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 15/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 23/24] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 16/24] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 21/24] RISC-V: Remove support for adhoc X_COP interrupt,
Michael Clark <=
- [Qemu-devel] [PULL 22/24] RISC-V: Convert cpu definition towards future model, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 24/24] RISC-V: Remove erroneous comment from translate.c, Michael Clark, 2018/03/21
- Re: [Qemu-devel] [PULL 00/24] RISC-V: Post-merge spec conformance and cleanup v5, Michael Clark, 2018/03/24