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[Qemu-devel] [PULL 11/19] target/arm: Allow EL change hooks to do IO
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 11/19] target/arm: Allow EL change hooks to do IO |
Date: |
Thu, 26 Apr 2018 11:47:07 +0100 |
From: Aaron Lindsay <address@hidden>
During code generation, surround CPSR writes and exception returns which
call the EL change hooks with gen_io_start/end. The immediate need is
for the PMU to access the clock and icount during EL change to support
mode filtering.
Signed-off-by: Aaron Lindsay <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 6 ++++++
target/arm/translate.c | 12 ++++++++++++
2 files changed, 18 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c91329249d..bff4e13bf6 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1930,7 +1930,13 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t
insn)
unallocated_encoding(s);
return;
}
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_exception_return(cpu_env);
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ }
/* Must exit loop to check un-masked IRQs */
s->base.is_jmp = DISAS_EXIT;
return;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index db1ce6510a..9bc2ce1a0b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4548,7 +4548,13 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc,
TCGv_i32 cpsr)
* appropriately depending on the new Thumb bit, so it must
* be called after storing the new PC.
*/
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_cpsr_write_eret(cpu_env, cpsr);
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ }
tcg_temp_free_i32(cpsr);
/* Must exit loop to check un-masked IRQs */
s->base.is_jmp = DISAS_EXIT;
@@ -9843,7 +9849,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int
insn)
if (exc_return) {
/* Restore CPSR from SPSR. */
tmp = load_cpu_field(spsr);
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_cpsr_write_eret(cpu_env, tmp);
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ }
tcg_temp_free_i32(tmp);
/* Must exit loop to check un-masked IRQs */
s->base.is_jmp = DISAS_EXIT;
--
2.17.0
- [Qemu-devel] [PULL 00/19] target-arm queue, Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 07/19] target/arm: Mask PMU register writes based on PMCR_EL0.N, Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 12/19] target/arm: Fix bitmask for PMCCFILTR writes, Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 10/19] target/arm: Add pre-EL change hooks, Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 11/19] target/arm: Allow EL change hooks to do IO,
Peter Maydell <=
- [Qemu-devel] [PULL 06/19] target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0, Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 14/19] hw/arm/raspi: Don't bother setting default_cpu_type, Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 09/19] target/arm: Support multiple EL change hooks, Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 13/19] target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide, Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 04/19] target/arm: Use v7m_stack_read() for reading the frame signature, Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 15/19] hw/arm/highbank: don't make sysram 'nomigrate', Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 02/19] arm: always start from first_cpu when registering loader cpu reset callback, Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 01/19] device_tree: Increase FDT_MAX_SIZE to 1 MiB, Peter Maydell, 2018/04/26