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[Qemu-devel] [PULL 13/16] target/arm: Implement FMOV (immediate) for fp1
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 13/16] target/arm: Implement FMOV (immediate) for fp16 |
Date: |
Tue, 15 May 2018 15:07:04 +0100 |
From: Alex Bennée <address@hidden>
All the hard work is already done by vfp_expand_imm, we just need to
make sure we pick up the correct size.
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[rth: Merge unallocated_encoding check with TCGMemOp conversion.]
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 9dacb583ae..35997969b4 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5674,11 +5674,25 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
{
int rd = extract32(insn, 0, 5);
int imm8 = extract32(insn, 13, 8);
- int is_double = extract32(insn, 22, 2);
+ int type = extract32(insn, 22, 2);
uint64_t imm;
TCGv_i64 tcg_res;
+ TCGMemOp sz;
- if (is_double > 1) {
+ switch (type) {
+ case 0:
+ sz = MO_32;
+ break;
+ case 1:
+ sz = MO_64;
+ break;
+ case 3:
+ sz = MO_16;
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+ break;
+ }
+ /* fallthru */
+ default:
unallocated_encoding(s);
return;
}
@@ -5687,7 +5701,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
return;
}
- imm = vfp_expand_imm(MO_32 + is_double, imm8);
+ imm = vfp_expand_imm(sz, imm8);
tcg_res = tcg_const_i64(imm);
write_fp_dreg(s, rd, tcg_res);
--
2.17.0
- [Qemu-devel] [PULL 06/16] target/arm: Implement FCVT (scalar, integer) for fp16, (continued)
- [Qemu-devel] [PULL 06/16] target/arm: Implement FCVT (scalar, integer) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 03/16] target/arm: Fix fp_status_f16 tininess before rounding, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 12/16] target/arm: Implement FCSEL for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 01/16] fpu/softfloat: int_to_float ensure r fully initialised, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 11/16] target/arm: Implement FCMP for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 10/16] target/arm: Implement FP data-processing (3 source) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 08/16] target/arm: Introduce and use read_fp_hreg, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 09/16] target/arm: Implement FP data-processing (2 source) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 02/16] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT), Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 05/16] target/arm: Early exit after unallocated_encoding in disas_fp_int_conv, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 13/16] target/arm: Implement FMOV (immediate) for fp16,
Peter Maydell <=
- [Qemu-devel] [PULL 16/16] tcg: Optionally log FPU state in TCG -d cpu logging, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 15/16] sdcard: Correct CRC16 offset in sd_function_switch(), Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 14/16] target/arm: Fix sqrt_f16 exception raising, Peter Maydell, 2018/05/15
- Re: [Qemu-devel] [PULL 00/16] target-arm queue, Peter Maydell, 2018/05/15