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[Qemu-devel] [PULL 10/32] target/arm: Implement SVE Bitwise Logical - Un
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/32] target/arm: Implement SVE Bitwise Logical - Unpredicated Group |
Date: |
Fri, 18 May 2018 18:19:47 +0100 |
From: Richard Henderson <address@hidden>
These were the instructions that were stubbed out when
introducing the decode skeleton.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-sve.c | 55 ++++++++++++++++++++++++++++++++------
1 file changed, 47 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index d323bd0b67..67d6db313e 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -42,22 +42,61 @@
* Implement all of the translator functions referenced by the decoder.
*/
-static bool trans_AND_zzz(DisasContext *s, arg_AND_zzz *a, uint32_t insn)
+/* Invoke a vector expander on two Zregs. */
+static bool do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn,
+ int esz, int rd, int rn)
{
- return false;
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn), vsz, vsz);
+ }
+ return true;
}
-static bool trans_ORR_zzz(DisasContext *s, arg_ORR_zzz *a, uint32_t insn)
+/* Invoke a vector expander on three Zregs. */
+static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn,
+ int esz, int rd, int rn, int rm)
{
- return false;
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm), vsz, vsz);
+ }
+ return true;
}
-static bool trans_EOR_zzz(DisasContext *s, arg_EOR_zzz *a, uint32_t insn)
+/* Invoke a vector move on two Zregs. */
+static bool do_mov_z(DisasContext *s, int rd, int rn)
{
- return false;
+ return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn);
}
-static bool trans_BIC_zzz(DisasContext *s, arg_BIC_zzz *a, uint32_t insn)
+/*
+ *** SVE Logical - Unpredicated Group
+ */
+
+static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
{
- return false;
+ return do_vector3_z(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm);
+}
+
+static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ if (a->rn == a->rm) { /* MOV */
+ return do_mov_z(s, a->rd, a->rn);
+ } else {
+ return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
+ }
+}
+
+static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ return do_vector3_z(s, tcg_gen_gvec_xor, 0, a->rd, a->rn, a->rm);
+}
+
+static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
}
--
2.17.0
- [Qemu-devel] [PULL 07/32] hw/arm/smmu-common: Fix coverity issue in get_block_pte_address, (continued)
- [Qemu-devel] [PULL 07/32] hw/arm/smmu-common: Fix coverity issue in get_block_pte_address, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 09/32] target/arm: Add SVE decode skeleton, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 06/32] hw/arm/smmuv3: Fix Coverity issue in smmuv3_record_event, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 01/32] target/arm: Add "ARM_CP_NO_GDB" as a new bit field for ARMCPRegInfo type, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 04/32] xlnx-zdma: Add a model of the Xilinx ZynqMP generic DMA, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 08/32] target/arm: Introduce translate-a64.h, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 11/32] target/arm: Implement SVE load vector/predicate, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 19/32] target/arm: Implement SVE bitwise shift by wide elements (predicated), Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 12/32] target/arm: Implement SVE predicate test, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 13/32] target/arm: Implement SVE Predicate Logical Operations Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 10/32] target/arm: Implement SVE Bitwise Logical - Unpredicated Group,
Peter Maydell <=
- [Qemu-devel] [PULL 18/32] target/arm: Implement SVE bitwise shift by vector (predicated), Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 24/32] target/arm: Implement SVE Stack Allocation Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 20/32] target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 14/32] target/arm: Implement SVE Predicate Misc Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 16/32] target/arm: Implement SVE Integer Reduction Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 15/32] target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 23/32] target/arm: Implement SVE Index Generation Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 17/32] target/arm: Implement SVE bitwise shift by immediate (predicated), Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 21/32] target/arm: Implement SVE Integer Multiply-Add Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 30/32] target/arm: Implement SVE Bitwise Immediate Group, Peter Maydell, 2018/05/18