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[Qemu-devel] [PULL 24/32] target/arm: Implement SVE Stack Allocation Gro
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 24/32] target/arm: Implement SVE Stack Allocation Group |
Date: |
Fri, 18 May 2018 18:20:01 +0100 |
From: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-sve.c | 27 +++++++++++++++++++++++++++
target/arm/sve.decode | 12 ++++++++++++
2 files changed, 39 insertions(+)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index e3a8e9506e..f95efa3c72 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -781,6 +781,33 @@ static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr
*a, uint32_t insn)
return true;
}
+/*
+ *** SVE Stack Allocation Group
+ */
+
+static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a, uint32_t insn)
+{
+ TCGv_i64 rd = cpu_reg_sp(s, a->rd);
+ TCGv_i64 rn = cpu_reg_sp(s, a->rn);
+ tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s));
+ return true;
+}
+
+static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a, uint32_t insn)
+{
+ TCGv_i64 rd = cpu_reg_sp(s, a->rd);
+ TCGv_i64 rn = cpu_reg_sp(s, a->rn);
+ tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s));
+ return true;
+}
+
+static bool trans_RDVL(DisasContext *s, arg_RDVL *a, uint32_t insn)
+{
+ TCGv_i64 reg = cpu_reg(s, a->rd);
+ tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s));
+ return true;
+}
+
/*
*** SVE Predicate Logical Operations Group
*/
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 4f9f64f5ab..9d5c061165 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -84,6 +84,9 @@
# One register operand, with governing predicate, vector element size
@rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
+# Two register operands with a 6-bit signed immediate.
address@hidden ........ ... rn:5 ..... imm:s6 rd:5 &rri
+
# Two register operand, one immediate operand, with predicate,
# element size encoded as TSZHL. User must fill in imm.
@rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \
@@ -238,6 +241,15 @@ INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
# SVE index generation (register start, register increment)
INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm
+### SVE Stack Allocation Group
+
+# SVE stack frame adjustment
+ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6
+ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6
+
+# SVE stack frame size
+RDVL 00000100 101 11111 01010 imm:s6 rd:5
+
### SVE Predicate Logical Operations Group
# SVE predicate logical operations
--
2.17.0
- [Qemu-devel] [PULL 06/32] hw/arm/smmuv3: Fix Coverity issue in smmuv3_record_event, (continued)
- [Qemu-devel] [PULL 06/32] hw/arm/smmuv3: Fix Coverity issue in smmuv3_record_event, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 01/32] target/arm: Add "ARM_CP_NO_GDB" as a new bit field for ARMCPRegInfo type, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 04/32] xlnx-zdma: Add a model of the Xilinx ZynqMP generic DMA, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 08/32] target/arm: Introduce translate-a64.h, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 11/32] target/arm: Implement SVE load vector/predicate, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 19/32] target/arm: Implement SVE bitwise shift by wide elements (predicated), Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 12/32] target/arm: Implement SVE predicate test, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 13/32] target/arm: Implement SVE Predicate Logical Operations Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 10/32] target/arm: Implement SVE Bitwise Logical - Unpredicated Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 18/32] target/arm: Implement SVE bitwise shift by vector (predicated), Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 24/32] target/arm: Implement SVE Stack Allocation Group,
Peter Maydell <=
- [Qemu-devel] [PULL 20/32] target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 14/32] target/arm: Implement SVE Predicate Misc Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 16/32] target/arm: Implement SVE Integer Reduction Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 15/32] target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 23/32] target/arm: Implement SVE Index Generation Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 17/32] target/arm: Implement SVE bitwise shift by immediate (predicated), Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 21/32] target/arm: Implement SVE Integer Multiply-Add Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 30/32] target/arm: Implement SVE Bitwise Immediate Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 22/32] target/arm: Implement SVE Integer Arithmetic - Unpredicated Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 29/32] target/arm: Implement SVE Element Count Group, Peter Maydell, 2018/05/18