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[Qemu-devel] [PATCH v1 14/30] RISC-V: Add public API for the CSR dispatc
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v1 14/30] RISC-V: Add public API for the CSR dispatch table |
Date: |
Wed, 23 May 2018 12:15:01 +1200 |
This allows hardware and/or derived cpu instances
to override or implement new CSR operations.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
---
target/riscv/cpu.h | 18 ++++++++++++++++++
target/riscv/csr.c | 35 ++++++++++++++++++-----------------
2 files changed, 36 insertions(+), 17 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 242a8fcbe180..1ade90d23bbc 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -307,6 +307,24 @@ static inline target_ulong csr_read_helper(CPURISCVState
*env, int csrno)
return val;
}
+typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno);
+typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
+ target_ulong *ret_value);
+typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
+ target_ulong new_value);
+typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
+ target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
+
+typedef struct {
+ riscv_csr_predicate_fn predicate;
+ riscv_csr_read_fn read;
+ riscv_csr_write_fn write;
+ riscv_csr_op_fn op;
+} riscv_csr_operations;
+
+void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
+void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
+
#include "exec/cpu-all.h"
#endif /* RISCV_CPU_H */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 509215327243..0f886e04b130 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -23,28 +23,29 @@
#include "qemu/main-loop.h"
#include "exec/exec-all.h"
+/* CSR function table */
-/* Control and Status Register function table forward declaration */
+static riscv_csr_operations csr_ops[];
-typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno);
-typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
- target_ulong *ret_value);
-typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
- target_ulong new_value);
-typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
- target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
+/* CSR function table constants */
-typedef struct {
- riscv_csr_predicate_fn predicate;
- riscv_csr_read_fn read;
- riscv_csr_write_fn write;
- riscv_csr_op_fn op;
-} riscv_csr_operations;
+enum {
+ CSR_TABLE_SIZE = 0xfff
+};
+
+/* CSR function table public API */
-static const riscv_csr_operations csr_ops[];
+void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
+{
+ *ops = csr_ops[csrno & CSR_TABLE_SIZE];
+}
+void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
+{
+ csr_ops[csrno & CSR_TABLE_SIZE] = *ops;
+}
-/* Predicates */
+/* CSR function table predicates (private) */
static int fs(CPURISCVState *env, int csrno)
{
@@ -784,7 +785,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong
*ret_value,
/* Control and Status Register function table */
-static const riscv_csr_operations csr_ops[0xfff] = {
+static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* User Floating-Point CSRs */
[CSR_FFLAGS] = { fs, read_fflags, write_fflags },
[CSR_FRM] = { fs, read_frm, write_frm },
--
2.7.0
- Re: [Qemu-devel] [PATCH v1 09/30] RISC-V: Implement atomic mip/sip CSR updates, (continued)
- [Qemu-devel] [PATCH v1 10/30] RISC-V: Implement existential predicates for CSRs, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 08/30] RISC-V: Implement modular CSR helper interface, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 11/30] RISC-V: Split out mstatus_fs from tb_flags, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 12/30] RISC-V: Mark mstatus.fs dirty, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 13/30] RISC-V: Implement mstatus.TSR/TW/TVM, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 14/30] RISC-V: Add public API for the CSR dispatch table,
Michael Clark <=
- [Qemu-devel] [PATCH v1 15/30] RISC-V: Add hartid and \n to interrupt logging, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 16/30] RISC-V: Use riscv prefix consistently on cpu helpers, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 17/30] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 18/30] RISC-V: Add missing free for plic_hart_config, Michael Clark, 2018/05/22